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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-07-26 01:54:34 +0200
committerMartin Roth <martinroth@google.com>2016-08-02 23:35:49 +0200
commitcc5be8b72ba5b072030fdd1d382d7156da43114f (patch)
treecb94bc583e87b6c58bdf675fdec363003d316227 /src
parentaded214e74bcb63990d69551bec7ab03c6785b08 (diff)
downloadcoreboot-cc5be8b72ba5b072030fdd1d382d7156da43114f.tar.xz
arch/riscv: Add include/arch/barrier.h
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/riscv/include/arch/barrier.h39
-rw-r--r--src/arch/riscv/include/atomic.h1
-rw-r--r--src/arch/riscv/virtual_memory.c5
-rw-r--r--src/mainboard/emulation/qemu-riscv/qemu_util.c5
-rw-r--r--src/mainboard/emulation/spike-riscv/spike_util.c1
5 files changed, 46 insertions, 5 deletions
diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h
new file mode 100644
index 0000000000..257e2a2bc3
--- /dev/null
+++ b/src/arch/riscv/include/arch/barrier.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright 2016 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ARCH_BARRIER_H_
+#define __ARCH_BARRIER_H__
+
+static inline void mb(void) { asm volatile("fence"); }
+static inline void rmb(void) { asm volatile("fence"); }
+static inline void wmb(void) { asm volatile("fence"); }
+
+#endif /* __ARCH_BARRIER_H__ */
diff --git a/src/arch/riscv/include/atomic.h b/src/arch/riscv/include/atomic.h
index df455b9e5b..8f10b9dfa4 100644
--- a/src/arch/riscv/include/atomic.h
+++ b/src/arch/riscv/include/atomic.h
@@ -36,7 +36,6 @@
typedef struct { int lock; } spinlock_t;
#define SPINLOCK_INIT {0}
-#define mb() __sync_synchronize()
#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index cda9057939..f0cd5f656a 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -14,11 +14,12 @@
* GNU General Public License for more details.
*/
-#include <vm.h>
+#include <arch/barrier.h>
#include <arch/encoding.h>
#include <atomic.h>
-#include <stdint.h>
#include <console/console.h>
+#include <stdint.h>
+#include <vm.h>
pte_t* root_page_table;
diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c
index fca7d56ed0..3c2941ce72 100644
--- a/src/mainboard/emulation/qemu-riscv/qemu_util.c
+++ b/src/mainboard/emulation/qemu-riscv/qemu_util.c
@@ -25,11 +25,12 @@
* MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*/
-#include <spike_util.h>
+#include <arch/barrier.h>
#include <arch/errno.h>
#include <atomic.h>
-#include <string.h>
#include <console/console.h>
+#include <spike_util.h>
+#include <string.h>
uintptr_t translate_address(uintptr_t vAddr) {
// TODO: implement the page table translation algorithm
diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c
index 358cb4428e..f0f5301814 100644
--- a/src/mainboard/emulation/spike-riscv/spike_util.c
+++ b/src/mainboard/emulation/spike-riscv/spike_util.c
@@ -26,6 +26,7 @@
*/
#include <spike_util.h>
+#include <arch/barrier.h>
#include <arch/errno.h>
#include <atomic.h>
#include <string.h>