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authorArthur Heymans <arthur@aheymans.xyz>2018-12-30 12:49:21 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-01-03 22:32:50 +0000
commitcd366349947cfe0a056a5913cca6b5151c32e8f6 (patch)
tree2e68f7dff7fee1cfd69955aaff3350660a0033f4 /src
parentd0cc3bc5ce36c35d8d69fd4a384abc41ce385d30 (diff)
downloadcoreboot-cd366349947cfe0a056a5913cca6b5151c32e8f6.tar.xz
sb/intel/bd82x6x: Move pcie ACPI code to a common place
Change-Id: I45144f9c397ff9a0be011990ba33db9ffef351e7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/pch.asl2
-rw-r--r--src/southbridge/intel/common/acpi/pcie.asl (renamed from src/southbridge/intel/bd82x6x/acpi/pcie.asl)0
-rw-r--r--src/southbridge/intel/common/acpi/pcie_port.asl (renamed from src/southbridge/intel/bd82x6x/acpi/pcie_port.asl)0
3 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index a068bc039c..d3aa7a4406 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -238,7 +238,7 @@ Scope(\)
#include "audio.asl"
// PCI Express Ports 0:1c.x
-#include "pcie.asl"
+#include <southbridge/intel/common/acpi/pcie.asl>
// USB EHCI 0:1d.0 and 0:1a.0, XHCI 0:14.0
#include "usb.asl"
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl
index d7842cd677..d7842cd677 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl
+++ b/src/southbridge/intel/common/acpi/pcie.asl
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl
index 4e04ab2338..4e04ab2338 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl
+++ b/src/southbridge/intel/common/acpi/pcie_port.asl