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authorAlexis Savery <asavery@chromium.org>2019-10-25 16:14:49 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-11-12 18:28:07 +0000
commitcd3c3167df7b00938f9a70933bdf2b9795655bdf (patch)
tree3226eed36be3c47bfa1f29d6293133be593f3775 /src
parentdf9cdcfc383ac38c2238fd6d640c9260028906f7 (diff)
downloadcoreboot-cd3c3167df7b00938f9a70933bdf2b9795655bdf.tar.xz
mainboard/google/hatch: Create helios_diskswap variant
Created helios_diskswap as a variant of helios (hatch variant). BUG=b:143378037 BRANCH=None TEST=none Change-Id: I6536b3908ec569e1ac42ea7c5be85701012ab177 Signed-off-by: Alexis Savery <asavery@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/Kconfig3
-rw-r--r--src/mainboard/google/hatch/Kconfig.name7
-rw-r--r--src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb209
3 files changed, 219 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 8488762eef..6c0a94afe6 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -91,6 +91,7 @@ config MAINBOARD_PART_NUMBER
default "Dratini" if BOARD_GOOGLE_DRATINI
default "Hatch" if BOARD_GOOGLE_HATCH
default "Helios" if BOARD_GOOGLE_HELIOS
+ default "Helios_Diskswap" if BOARD_GOOGLE_HELIOS_DISKSWAP
default "Kindred" if BOARD_GOOGLE_KINDRED
default "Kohaku" if BOARD_GOOGLE_KOHAKU
default "Puff" if BOARD_GOOGLE_PUFF
@@ -105,6 +106,7 @@ config MAX_CPUS
config OVERRIDE_DEVICETREE
string
+ default "variants/helios_diskswap/overridetree.cb" if BOARD_GOOGLE_HELIOS_DISKSWAP
default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config TPM_TIS_ACPI_INTERRUPT
@@ -117,6 +119,7 @@ config VARIANT_DIR
default "dratini" if BOARD_GOOGLE_DRATINI
default "hatch" if BOARD_GOOGLE_HATCH
default "helios" if BOARD_GOOGLE_HELIOS
+ default "helios" if BOARD_GOOGLE_HELIOS_DISKSWAP
default "kindred" if BOARD_GOOGLE_KINDRED
default "kohaku" if BOARD_GOOGLE_KOHAKU
default "puff" if BOARD_GOOGLE_PUFF
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index 2051e0f12a..ec12096269 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -38,3 +38,10 @@ config BOARD_GOOGLE_PUFF
select BOARD_GOOGLE_BASEBOARD_HATCH
select BOARD_ROMSIZE_KB_32768
select ROMSTAGE_SPD_SMBUS
+
+config BOARD_GOOGLE_HELIOS_DISKSWAP
+ bool "-> Helios_Diskswap"
+ select BOARD_GOOGLE_BASEBOARD_HATCH
+ select BOARD_ROMSIZE_KB_16384
+ select CHROMEOS_DSM_CALIB
+ select DRIVERS_I2C_RT1011
diff --git a/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
new file mode 100644
index 0000000000..3bbf232a93
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/helios_diskswap/overridetree.cb
@@ -0,0 +1,209 @@
+chip soc/intel/cannonlake
+ register "tdp_pl1_override" = "13"
+ register "tdp_pl2_override" = "64"
+
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # Enable Root port 9(x2) for NVMe.
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ # RP 9 uses CLK SRC 1
+ register "PcieClkSrcUsage[1]" = "8"
+ # ClkReq-to-ClkSrc mapping for CLK SRC 1
+ register "PcieClkSrcClkReq[1]" = "1"
+
+ # Enable Root port 11(x2) for NVMe.
+ register "PcieRpEnable[10]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+ # RP 11 uses CLK SRC 2
+ register "PcieClkSrcUsage[2]" = "10"
+ # ClkReq-to-ClkSrc mapping for CLK SRC 2
+ register "PcieClkSrcClkReq[2]" = "1"
+
+ # No PCIe WiFi
+ register "PcieRpEnable[13]" = "0"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI1 | FP MCU |
+ #| I2C0 | Trackpad |
+ #| I2C1 | Touchscreen |
+ #| I2C4 | Audio |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 50,
+ .fall_time_ns = 15,
+ .data_hold_time_ns = 330,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 60,
+ .fall_time_ns = 25,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 150,
+ .fall_time_ns = 150,
+ },
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ .rise_time_ns = 120,
+ .fall_time_ns = 120,
+ },
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ }"
+
+ device domain 0 on
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ # No Type-A port
+ device usb 2.2 off end
+ end
+ chip drivers/usb/acpi
+ # No Type-A Port
+ device usb 2.3 off end
+ end
+ chip drivers/usb/acpi
+ # No WWAN
+ device usb 2.5 off end
+ end
+ chip drivers/usb/acpi
+ # No WWAN
+ device usb 3.4 off end
+ end
+ end
+ end
+ end
+
+ # Native SD Card interface unused
+ device pci 14.5 off end
+
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+ register "wake" = "GPE0_DW0_21"
+ device i2c 15 on end
+ end
+ end
+
+ device pci 15.1 on
+ chip drivers/i2c/hid
+ register "generic.hid" = ""GDIX0000""
+ register "generic.desc" = ""Goodix Touchscreen""
+ register "generic.irq" =
+ "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
+ register "generic.probed" = "1"
+ register "generic.reset_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
+ register "generic.reset_delay_ms" = "500"
+ register "generic.reset_off_delay_ms" = "1"
+ register "generic.enable_gpio" =
+ "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)"
+ register "generic.enable_delay_ms" = "10"
+ register "generic.enable_off_delay_ms" = "1"
+ register "generic.has_power_resource" = "1"
+ register "hid_desc_reg_offset" = "0x01"
+ device i2c 5d on end
+ end
+ chip drivers/generic/gpio_keys
+ register "name" = ""PENH""
+ register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
+ register "key.wake" = "GPE0_DW0_08"
+ register "key.wakeup_event_action" = "EV_ACT_ASSERTED"
+ register "key.dev_name" = ""EJCT""
+ register "key.linux_code" = "SW_PEN_INSERTED"
+ register "key.linux_input_type" = "EV_SW"
+ register "key.label" = ""pen_eject""
+ device generic 0 on end
+ end
+ end # I2C 1
+
+ # I2C #2 unused
+ device pci 15.2 off end
+
+ # I2C #3 unused
+ device pci 15.3 off end
+
+ device pci 19.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""10EC5682""
+ register "name" = ""RT58""
+ register "desc" = ""Realtek RT5682""
+ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
+ register "property_count" = "1"
+ # Set the jd_src to RT5668_JD1 for jack detection
+ register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+ register "property_list[0].name" = ""realtek,jd-src""
+ register "property_list[0].integer" = "1"
+ device i2c 1a on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC1011""
+ register "desc" = ""RT1011 Tweeter Left Speaker Amp""
+ register "uid" = "0"
+ register "name" = ""TL""
+ device i2c 38 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC1011""
+ register "desc" = ""RT1011 Tweeter Right Speaker Amp""
+ register "uid" = "1"
+ register "name" = ""TR""
+ device i2c 39 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC1011""
+ register "desc" = ""RT1011 Woofer Left Speaker Amp""
+ register "uid" = "2"
+ register "name" = ""WL""
+ device i2c 3a on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""10EC1011""
+ register "desc" = ""RT1011 Woofer Right Speaker Amp""
+ register "uid" = "3"
+ register "name" = ""WR""
+ device i2c 3b on end
+ end
+ end #I2C #4
+
+ device pci 1d.0 on end # PCI Express Port 9 (X2 NVMe)
+ device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
+
+ device pci 1e.3 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)"
+ register "wake" = "GPE0_DW0_23"
+ device spi 1 on end
+ end # FPMCU
+ end # GSPI #1
+ end
+end