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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-06-03 08:40:34 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-18 14:42:19 +0200
commitcf5ac3d7ef1a0f4876f1df7368d19d57d168bae4 (patch)
tree22d2c603cef2ac2b014153c33e4fbd7466e7b271 /src
parent031cf214c6626677312f25cd17ed391d8aec4b79 (diff)
downloadcoreboot-cf5ac3d7ef1a0f4876f1df7368d19d57d168bae4.tar.xz
src/superio/smsc/lpc47m15x: Avoid #include early_serial.c
Provide proper header and function type-signatures for Super I/O romstage component. Fix mainboard's bogous romstage component to match. Change-Id: Icd02199690d0c428b2daadf702d50714dc367692 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5924 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c38
-rw-r--r--src/superio/smsc/lpc47m15x/Makefile.inc1
-rw-r--r--src/superio/smsc/lpc47m15x/early_serial.c5
-rw-r--r--src/superio/smsc/lpc47m15x/lpc47m15x.h11
4 files changed, 19 insertions, 36 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 586e03502e..fbec052fba 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -28,16 +28,16 @@
#include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h>
-#include "superio/smsc/lpc47m15x/lpc47m15x.h"
+#include <superio/smsc/lpc47m15x/lpc47m15x.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/bist.h>
-#include "superio/smsc/lpc47m15x/early_serial.c"
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
+#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
void setup_ich7_gpios(void)
{
@@ -68,34 +68,6 @@ static void ich7_enable_lpc(void)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c0681);
}
-/* This box has two superios, so enabling serial becomes slightly excessive.
- * We disable a lot of stuff to make sure that there are no conflicts between
- * the two. Also set up the GPIOs from the beginning. This is the "no schematic
- * but safe anyways" method.
- */
-static void early_superio_config_lpc47m15x(void)
-{
- device_t dev;
-
- dev=PNP_DEV(0x2e, LPC47M15X_SP1);
- pnp_enter_conf_state(dev);
-
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
- pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
- pnp_set_enable(dev, 1);
-
- /* Enable SuperIO PM */
- dev=PNP_DEV(0x2e, LPC47M15X_PME);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, 0x680);
- pnp_set_enable(dev, 1);
-
- pnp_exit_conf_state(dev);
-}
-
static void rcba_config(void)
{
/* Set up virtual channel 0 */
@@ -194,7 +166,9 @@ void main(unsigned long bist)
enable_lapic();
ich7_enable_lpc();
- early_superio_config_lpc47m15x();
+ /* Enable SuperIO PM */
+ lpc47m15x_enable_serial(PME_DEV, 0x680);
+ lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
/* Set up the console */
console_init();
diff --git a/src/superio/smsc/lpc47m15x/Makefile.inc b/src/superio/smsc/lpc47m15x/Makefile.inc
index c43e037a37..610d87cbce 100644
--- a/src/superio/smsc/lpc47m15x/Makefile.inc
+++ b/src/superio/smsc/lpc47m15x/Makefile.inc
@@ -17,4 +17,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+romstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c
ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c
diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c
index 7d75baecbe..5686f52106 100644
--- a/src/superio/smsc/lpc47m15x/early_serial.c
+++ b/src/superio/smsc/lpc47m15x/early_serial.c
@@ -20,6 +20,9 @@
/* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */
#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+
#include "lpc47m15x.h"
static void pnp_enter_conf_state(device_t dev)
@@ -34,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev)
outb(0xaa, port);
}
-static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase)
+void lpc47m15x_enable_serial(device_t dev, u16 iobase)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x.h b/src/superio/smsc/lpc47m15x/lpc47m15x.h
index 04f1729abe..32cff48f01 100644
--- a/src/superio/smsc/lpc47m15x/lpc47m15x.h
+++ b/src/superio/smsc/lpc47m15x/lpc47m15x.h
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef SUPERIO_SMSC_LPC47M15X_LPC47M15X_H
-#define SUPERIO_SMSC_LPC47M15X_LPC47M15X_H
+#ifndef SUPERIO_SMSC_LPC47M15X_H
+#define SUPERIO_SMSC_LPC47M15X_H
#define LPC47M15X_FDC 0 /* Floppy */
#define LPC47M15X_PP 3 /* Parallel Port */
@@ -31,4 +31,9 @@
#define LPC47M15X2_MAX_CONFIG_REGISTER 0x5F
-#endif
+#include <arch/io.h>
+#include <stdint.h>
+
+void lpc47m15x_enable_serial(device_t dev, u16 iobase);
+
+#endif /* SUPERIO_SMSC_LPC47M15X_H */