diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-31 13:40:15 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-05 01:54:55 +0200 |
| commit | d52636113aa2ff7da27f710db9b8a53ac5de6ed2 (patch) | |
| tree | da54268eb392b4c18ad8849a2ba6351bb364352d /src | |
| parent | f26fc0f28bf62dd34533aea47105f174ee794e66 (diff) | |
| download | coreboot-d52636113aa2ff7da27f710db9b8a53ac5de6ed2.tar.xz | |
soc/intel/quark: Disable FSP serial output
Disable FSP output when CONFIG_DEFAULT_CONSOLE_LOGLEVEL is not set to 8
(BIOS_SPEW). Use the console log level to choose between the serial
port address and NULL and pass it to FSP for the serial port address.
TEST=Build and run on Galileo Gen2.
Change-Id: I5498aad218524c211082d85d0ae9aacaf08a80f6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16005
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp1_1.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c index 16d1d063c3..5ba2174628 100644 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -120,7 +120,8 @@ void soc_memory_init_params(struct romstage_params *params, upd->RankMask = config->RankMask; upd->RmuBaseAddress = (uintptr_t)rmu_file; upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW) + ? UART_BASE_ADDRESS : 0; upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal; diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index af05856ab0..6ca6a4c011 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -161,7 +161,8 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd) upd->RankMask = config->RankMask; upd->RmuBaseAddress = (uintptr_t)rmu_file; upd->RmuLength = rmu_file_len; - upd->SerialPortBaseAddress = UART_BASE_ADDRESS; + upd->SerialPortBaseAddress = console_log_level(BIOS_SPEW) + ? UART_BASE_ADDRESS : 0; upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ? config->SmmTsegSize : 0; upd->SocRdOdtVal = config->SocRdOdtVal; |