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authorWard Vandewege <ward@gnu.org>2008-02-01 23:07:04 +0000
committerWard Vandewege <ward@gnu.org>2008-02-01 23:07:04 +0000
commitd8a74c95d175f606aa50fa18ff30e4bed1795053 (patch)
tree0191f868b5ceb7ec459fa3d98eb2c2c85ef1e640 /src
parentf3dd1b7e57e0ed6c52889ef14a97fb135c2bbc37 (diff)
downloadcoreboot-d8a74c95d175f606aa50fa18ff30e4bed1795053.tar.xz
This patch reverses an erroneous change that sneaked in during r2972, and broke
flashrom on the plcc-based rev 1 and 1.1 of the Gigabyte m57sli-s4 board. Signed-off-by: Ward Vandewege <ward@gnu.org> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3087 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/gigabyte/m57sli/Config.lb4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb
index 20eb4b509e..88eb4d3d1f 100644
--- a/src/mainboard/gigabyte/m57sli/Config.lb
+++ b/src/mainboard/gigabyte/m57sli/Config.lb
@@ -309,8 +309,8 @@ chip northbridge/amd/amdk8/root_complex
#irq 0xc3 = 0x0
# SIO pin set 1 input mode
#irq 0xc8 = 0x0
- # SIO pin set 2 mixed input/output mode
- irq 0xc9 = 0x40
+ # SIO pin set 2 input mode
+ irq 0xc9 = 0x0
# SIO pin set 4 input mode
#irq 0xcb = 0x0
# Generate SMI# on EC IRQ