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authorJoseph Smith <joe@settoplinux.org>2008-05-15 13:44:33 +0000
committerJoseph Smith <joe@smittys.pointclark.net>2008-05-15 13:44:33 +0000
commitda69582ce45d4302cb0265b56a65f0787603a29a (patch)
treee541227a18973adabbed22dc8b10092a634d3d39 /src
parente3da00de8d304e80fb32c0e66ce1c85e7fe4da93 (diff)
downloadcoreboot-da69582ce45d4302cb0265b56a65f0787603a29a.tar.xz
This patch allows the RCA RM4100 to reboot. Upon rebooting in auto.c it detects if the memory is already initialized, if so it issues a hard reset through the southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3322 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/rca/rm4100/auto.c9
-rw-r--r--src/northbridge/intel/i82830/memory_initialized.c30
2 files changed, 38 insertions, 1 deletions
diff --git a/src/mainboard/rca/rm4100/auto.c b/src/mainboard/rca/rm4100/auto.c
index f4e05e9473..14c50cb78c 100644
--- a/src/mainboard/rca/rm4100/auto.c
+++ b/src/mainboard/rca/rm4100/auto.c
@@ -33,7 +33,9 @@
#include "ram/ramtest.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i82830/raminit.h"
+#include "northbridge/intel/i82830/memory_initialized.c"
#include "southbridge/intel/i82801xx/i82801xx.h"
+#include "southbridge/intel/i82801xx/i82801xx_reset.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include "spd_table.h"
@@ -95,6 +97,9 @@ static void main(unsigned long bist)
if (bist == 0)
early_mtrr_init();
+ if (memory_initialized()) {
+ hard_reset();
+ }
enable_smbus();
@@ -103,6 +108,9 @@ static void main(unsigned long bist)
uart_init();
console_init();
+ /* Prevent the TCO timer from rebooting us */
+ i82801xx_halt_tco_timer();
+
/* Halt if there was a built in self test failure. */
report_bist_failure(bist);
@@ -114,6 +122,5 @@ static void main(unsigned long bist)
/* ram_check(0, 640 * 1024); */
/* ram_check(130048 * 1024, 131072 * 1024); */
- i82801xx_halt_tco_timer();
ac97_io_enable();
}
diff --git a/src/northbridge/intel/i82830/memory_initialized.c b/src/northbridge/intel/i82830/memory_initialized.c
new file mode 100644
index 0000000000..d67d9ff2e7
--- /dev/null
+++ b/src/northbridge/intel/i82830/memory_initialized.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#include "i82830.h"
+#define NB_DEV PCI_DEV(0, 0, 0)
+
+static inline int memory_initialized(void)
+{
+ u32 drc;
+ drc = pci_read_config32(NB_DEV, DRC);
+ return (drc & (1<<29));
+}