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authorSumeet Pawnikar <sumeet.r.pawnikar@intel.com>2019-04-04 06:55:19 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-04-08 14:10:02 +0000
commitdb3ba1bc186c487157ba9161dfc965f3e22a026f (patch)
tree1205d423ad4b03498683bc7516fc5de29d84c794 /src
parenta2b7be7496bc8768d18e278d861765aa4025dfb4 (diff)
downloadcoreboot-db3ba1bc186c487157ba9161dfc965f3e22a026f.tar.xz
mb/mainboard/google/sarien/variants: Set correct tcc_offset value
Set new tcc_offset value to 10 degree C. This configures the Thermal Control Circuit (TCC) activation value to 90 degree C. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action when CPU temperature goes above 90 degree C. Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/sarien/variants/arcada/devicetree.cb2
-rw-r--r--src/mainboard/google/sarien/variants/sarien/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 4bf3736567..1507214f99 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -161,7 +161,7 @@ chip soc/intel/cannonlake
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
- register "tcc_offset" = "5"
+ register "tcc_offset" = "10"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index f04149f49e..e4a92a96d5 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -158,7 +158,7 @@ chip soc/intel/cannonlake
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
- register "tcc_offset" = "5"
+ register "tcc_offset" = "10"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,