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authorMarc Jones <marc.jones@amd.com>2007-06-14 17:00:50 +0000
committerJordan Crouse <jordan.crouse@amd.com>2007-06-14 17:00:50 +0000
commitdd55e86a52a98c1acae30bc699eaaa12f416de51 (patch)
treedac3c9990bb03f602b337bcdd833927e6522deac /src
parentd9e56e9cd3f5b4b35917c010de60369285bb39da (diff)
downloadcoreboot-dd55e86a52a98c1acae30bc699eaaa12f416de51.tar.xz
his patch fixes the CAS map for -.5 and -1 CAS settings. The -.5 setting should only shift the mask one bit, not two.
Signed-off-by: Marc Jones <marc.jones@amd.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/amd/lx/raminit.c47
1 files changed, 23 insertions, 24 deletions
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index a8555823f6..9981f58cae 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -151,7 +151,7 @@ static void checkDDRMax(void)
}
/* I don't think you need this check.
- if (spd_byte0 < 0xA0 || spd_byte0 < 0xA0){
+ if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
print_debug("DIMM overclocked. Check GeodeLink Speed\n");
POST_CODE(POST_PLL_MEM_FAIL);
__asm__ __volatile__("hlt\n");
@@ -231,7 +231,7 @@ static void setCAS(void)
;* Destroys: We really use everything !
;*****************************************************************************/
uint16_t glspeed, dimm_speed;
- uint8_t spd_byte, casmap0, casmap1;
+ uint8_t spd_byte, casmap0, casmap1, casmap_shift;
msr_t msr;
glspeed = GeodeLinkSpeed();
@@ -246,25 +246,24 @@ static void setCAS(void)
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) +
(spd_byte & 0x0F)));
if (dimm_speed >= glspeed) {
+ casmap_shift = 1; /* -.5 is a shift of 1 */
/* IF -1 timing is supported, check -1 timing > GeodeLink */
spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD);
if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
- if (dimm_speed <= glspeed) {
- /* set we can use -.5 timing but not -1 */
- spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
- /* just want bits in the lower byte since we have to cast to a 32 */
- casmap0 &= 0xFF << (--spd_byte);
+ if (dimm_speed >= glspeed) {
+ casmap_shift = 2; /* -1 is a shift of 2 */
}
- } /*MIN_CYCLE_10 !=0 */
+ } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
} else {
- /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
- spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
- /* just want bits in the lower byte since we have to cast to a 32 */
- casmap0 &= 0xFF << (spd_byte);
+ casmap_shift = 0;
}
- } /*MIN_CYCLE_05 !=0 */
+ } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
+ /* set the casmap based on the shift to limit possible CAS settings */
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap0);
+ /* just want bits in the lower byte since we have to cast to a 32 */
+ casmap0 &= 0xFF << (spd_byte - casmap_shift);
} else { /* No DIMM */
casmap0 = 0;
}
@@ -278,25 +277,25 @@ static void setCAS(void)
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
if (dimm_speed >= glspeed) {
+ casmap_shift = 1; /* -.5 is a shift of 1 */
/* IF -1 timing is supported, check -1 timing > GeodeLink */
spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD);
if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 2 * (10000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)));
- if (dimm_speed <= glspeed) {
- /* set we can use -.5 timing but not -1 */
- spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
- /* just want bits in the lower byte since we have to cast to a 32 */
- casmap1 &= 0xFF << (--spd_byte);
+ if (dimm_speed >= glspeed) {
+ casmap_shift = 2; /* -1 is a shift of 2 */
}
- } /*MIN_CYCLE_10 !=0 */
+ /* note that the -1 result doesn't need to change the available CAS map */
+ } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
} else {
- /* Timing_05 < GLspeed, can't use -.5 or -1 timing */
- spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
- /* just want bits in the lower byte since we have to cast to a 32 */
- casmap1 &= 0xFF << (spd_byte);
+ casmap_shift = 0;
}
- } /*MIN_CYCLE_05 !=0 */
+ } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
+ /* set the casmap based on the shift to limit possible CAS settings */
+ spd_byte = 31 - __builtin_clz((uint32_t) casmap1);
+ /* just want bits in the lower byte since we have to cast to a 32 */
+ casmap1 &= 0xFF << (spd_byte - casmap_shift);
} else { /* No DIMM */
casmap1 = 0;
}