diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-01-11 16:14:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:28:32 +0000 |
| commit | de2ab41fc43152b652af7c1f658b1c27926afd6c (patch) | |
| tree | 6313677b0de43ae3eb3e601a6fa66e1f8c0e8414 /src | |
| parent | cb18524b4a789195c78490fea9398178d4d043fe (diff) | |
| download | coreboot-de2ab41fc43152b652af7c1f658b1c27926afd6c.tar.xz | |
soc/intel/common: Move L1_substates_control to pcie_rp.h
L1_substates_control is common define. Move out of soc level.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I54574b606985e82d00beb1a61cce3097580366a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/pcie_rp.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 8 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 8 |
5 files changed, 16 insertions, 24 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 8e59c9ad5c..f23b9d2566 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/pcie_rp.h> #include <soc/gpe.h> #include <soc/pch.h> #include <soc/pci_devs.h> @@ -136,12 +137,7 @@ struct soc_intel_alderlake_config { uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS]; diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 578a600e5b..2030e72453 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -63,4 +63,12 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups); */ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups); +/* This enum is for passing into an FSP UPD, typically PcieRpL1Substates */ +enum L1_substates_control { + L1_SS_FSP_DEFAULT, + L1_SS_DISABLED, + L1_SS_L1_1, + L1_SS_L1_2, +}; + #endif /* SOC_INTEL_COMMON_BLOCK_PCIE_RP_H */ diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 37237bbbc1..1d97b36084 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/pcie_rp.h> #include <intelblocks/power_limit.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -116,12 +117,7 @@ struct soc_intel_elkhartlake_config { uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 3b813398a8..6e52efded3 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/pcie_rp.h> #include <intelblocks/power_limit.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -114,12 +115,7 @@ struct soc_intel_jasperlake_config { uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* SMBus */ uint8_t SmbusEnable; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 86e77da972..d3062cc720 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/pcie_rp.h> #include <intelblocks/power_limit.h> #include <soc/gpe.h> #include <soc/gpio.h> @@ -247,12 +248,7 @@ struct soc_intel_tigerlake_config { uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; /* PCIe RP L1 substate */ - enum L1_substates_control { - L1_SS_FSP_DEFAULT, - L1_SS_DISABLED, - L1_SS_L1_1, - L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; |