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authorMartin Roth <martinroth@google.com>2017-10-16 11:06:44 -0600
committerAaron Durbin <adurbin@chromium.org>2017-10-17 18:29:14 +0000
commitde897a6dba1bc6ce157aed8c00cc20642c5d6c59 (patch)
tree78a36e131fa8274bb496b53a2b67f7652f4316cf /src
parentefe1e2d2d458897995552c173ad826b52afd768d (diff)
downloadcoreboot-de897a6dba1bc6ce157aed8c00cc20642c5d6c59.tar.xz
soc/amd/stoneyridge: clean up chip.h
Remove obsolete register entries. BUG=None TEST=build Change-Id: Ia9beb9d42f0ee5d63d9e9073507fc606a9d45c46 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/chip.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h
index cd3bc74d90..4e1aa66eea 100644
--- a/src/soc/amd/stoneyridge/chip.h
+++ b/src/soc/amd/stoneyridge/chip.h
@@ -20,12 +20,6 @@
struct soc_amd_stoneyridge_config {
u8 spdAddrLookup[1][1][2];
- u32 ide0_enable : 1;
- u32 sata0_enable : 1;
- u32 boot_switch_sata_ide : 1;
- u32 hda_viddid;
- u8 gpp_configuration;
- u8 sd_mode;
};
typedef struct soc_amd_stoneyridge_config config_t;