mb/amd/lamar: Drop unmaintained ROMCC board

Remove unmaintained and unsupported old ROMCC board.
This board wasn't hooked up for build.

Change-Id: Iaa812dc66ddc14c24263a68e73115502ba5e2417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

21 files changed, 0 insertions, 1868 deletions

diff --git a/src/mainboard/amd/lamar/BiosCallOuts.c b/src/mainboard/amd/lamar/BiosCallOuts.c
deleted file mode 100644
index 30dc0d6d63..0000000000
--- a/src/mainboard/amd/lamar/BiosCallOuts.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/BiosCallOuts.h>
-#include <FchPlatform.h>
-#include <stdlib.h>
-#include <device/azalia.h>
-
-#include "imc.h"
-#include "hudson.h"
-
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
-
-const BIOS_CALLOUT_STRUCT BiosCallouts[] =
-{
-	{AGESA_READ_SPD,                 agesa_ReadSpd },
-	{AGESA_DO_RESET,                 agesa_Reset },
-	{AGESA_READ_SPD_RECOVERY,        agesa_NoopUnsupported },
-	{AGESA_RUNFUNC_ONAP,             agesa_RunFuncOnAp },
-	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
-	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
-	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
-	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
-};
-const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
-
-/**
- * Realtek ALC272 CODEC Verb Table
- */
-static const CODEC_ENTRY Alc272_VerbTbl[] = {
-	{ 0x11, 0x411111F0 },               /*        - S/PDIF Output 2         */
-	{ 0x12, 0x411111F0 },               /*        - Digital Mic 1/2 [GPIO0] */
-	{ 0x13, 0x411111F0 },               /*        - Digital Mic 3/4 [GPIO1] */
-	{ 0x14, 0x411111F0 },               /* Port D - Front Panel headphone   */
-	{ 0x15, 0x411111F0 },               /* Port A - Surround                */
-	{ 0x17, 0x411111F0 },               /* Port H - Mono                    */
-	{ 0x18,                             /* Port B - MIC - pink jack         */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
-			| (AZALIA_PINCFG_DEVICE_MICROPHONE << 20)
-			| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
-			| (AZALIA_PINCFG_COLOR_PINK << 12)
-			| (4 << 4)
-			| (0 << 0)
-	},
-	{ 0x19, 0x411111F0 },               /* Port F - Front Panel Mic        */
-	{ 0x1A,                             /* Port C - LineIn1 - blue jack    */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
-			| (AZALIA_PINCFG_DEVICE_LINEIN << 20)
-			| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
-			| (AZALIA_PINCFG_COLOR_BLUE << 12)
-			| (4 << 4)
-			| (0xF << 0)
-	},
-	{ 0x1B, 0x411111F0 },               /* Port E - Front Panel line-out   */
-	{ 0x1D, 0x40251E05 },               /* PC Beep - (internal)            */
-	{ 0x1E,                             /* S/PDIF - Internal Header        */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24)
-			| (AZALIA_PINCFG_DEVICE_SPDIF_OUT << 20)
-			| (AZALIA_PINCFG_CONN_RCA << 16)
-			| (AZALIA_PINCFG_COLOR_BLACK << 12)
-			| (1 << 4)
-			| (0 << 0)
-	},
-	{ 0x21,                             /* Port I - HPout - green jack     */
-			(AZALIA_PINCFG_PORT_JACK << 30)
-			| ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24)
-			| (AZALIA_PINCFG_DEVICE_HP_OUT << 20)
-			| (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16)
-			| (AZALIA_PINCFG_COLOR_GREEN << 12)
-			| (4 << 4)
-			| (0 << 0)
-	},
-	{ 0xFF, 0xFFFFFFFF },
-};
-
-static const CODEC_TBL_LIST CodecTableList[] =
-{
-	{0x10ec0272, (CODEC_ENTRY*)&Alc272_VerbTbl[0]},
-	{(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
-};
-
-#define FAN_INPUT_INTERNAL_DIODE	0
-#define FAN_INPUT_TEMP0			1
-#define FAN_INPUT_TEMP1			2
-#define FAN_INPUT_TEMP2			3
-#define FAN_INPUT_TEMP3			4
-#define FAN_INPUT_TEMP0_FILTER		5
-#define FAN_INPUT_ZERO			6
-#define FAN_INPUT_DISABLED		7
-
-#define FAN_AUTOMODE			(1 << 0)
-#define FAN_LINEARMODE			(1 << 1)
-#define FAN_STEPMODE			~(1 << 1)
-#define FAN_POLARITY_HIGH		(1 << 2)
-#define FAN_POLARITY_LOW		~(1 << 2)
-
-/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */
-#define FREQ_28KHZ			0x0
-#define FREQ_25KHZ			0x1
-#define FREQ_23KHZ			0x2
-#define FREQ_21KHZ			0x3
-#define FREQ_29KHZ			0x4
-#define FREQ_18KHZ			0x5
-#define FREQ_100HZ			0xF7
-#define FREQ_87HZ			0xF8
-#define FREQ_58HZ			0xF9
-#define FREQ_44HZ			0xFA
-#define FREQ_35HZ			0xFB
-#define FREQ_29HZ			0xFC
-#define FREQ_22HZ			0xFD
-#define FREQ_14HZ			0xFE
-#define FREQ_11HZ			0xFF
-
-/*
- * Hardware Monitor Fan Control
- * Hardware limitation:
- *  HWM will fail to read the input temperature via I2C if other
- *  software switches the I2C address.  AMD recommends using IMC
- *  to control fans, instead of HWM.
- */
-static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
-{
-	FCH_HWM_FAN_CTR oem_factl[5] = {
-		/*temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */
-		/* FanOUT0 Fan header J32 */
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		/* FanOUT1 Fan header J31*/
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-		{FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60,  0, 40, 65, 85, 0, 0},
-	};
-	LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof(FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader);
-
-	/* Enable IMC fan control. the recommended way */
-	if (CONFIG(HUDSON_IMC_FWM)) {
-		imc_reg_init();
-
-		/* HwMonitorEnable = TRUE &&  HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;       /* 0 disable, 1 enable TSI Auto Polling */
-
-		FchParams->Imc.ImcEnable = TRUE;
-		FchParams->Hwm.HwmControl = 1;	/* 1 IMC, 0 HWM */
-		FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC, 1 enable IMC, 0 following hw strap setting */
-
-		LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader);
-
-		/* Thermal Zone Parameter */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d;    /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;    /* 6 | BIT3 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 0x02;
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0x01;    /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0x00;
-
-		/* IMC Fan Policy temperature thresholds */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;    /* AC0 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c;    /* AC1 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32;    /* AC2 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff;    /* AC3 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0xff;    /* AC4 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0xff;    /* AC5 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0xff;    /* AC6 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0xff;    /* AC7 lowest threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0x4b;    /* critical threshold* in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00;
-
-		/* IMC Fan Policy PWM Settings */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0x5a;    /* AL0 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0x46;    /* AL1 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0x28;    /* AL2 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0xff;    /* AL3 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0xff;    /* AL4 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0xff;    /* AL5 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff;    /* AL6 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff;    /* AL7 percentage */
-
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;    /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0;
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0;
-
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01;    /* zone */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60;      /* AC0 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40;      /* AC1 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0;       /* AC2 threshold in Celsius */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0;       /* AC3 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0;       /* AC4 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0;       /* AC5 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0;       /* AC6 threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0;       /* AC7 lowest threshold in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0;       /* critical threshold* in Celsius, 0xFF is not define */
-		FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00;
-
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01;    /* Zone */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0;       /* AL0 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0;       /* AL1 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0;       /* AL2 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00;    /* AL3 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00;    /* AL4 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00;    /* AL5 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00;    /* AL6 percentage */
-		FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00;    /* AL7 percentage */
-
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2;     /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;     /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98;    /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2;
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0;
-
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3;     /* Zone */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;     /* BIT0 | BIT2 | BIT5 */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0;     /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0;
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0;       /* PWM stepping rate in unit of PWM level percentage */
-		FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0;
-
-		/* IMC Function */
-		FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;/* BIT0 | BIT4 |BIT8 */
-
-		/* NOTE:
-		 * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
-		 * AGESA put EcDefaultMessage as global data in ROM, so we can't override it.
-		 * so we remove it from AGESA code. Please See FchInitLateHwm.
-		 */
-	} else {
-		/* HWM fan control, using the alternative method */
-		FchParams->Imc.ImcEnable = FALSE;
-		FchParams->Hwm.HwMonitorEnable = TRUE;
-		FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */
-	}
-}
-
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such Azalia, SATA, IMC etc.
- */
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
-{
-	AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr;
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams =  (FCH_RESET_DATA_BLOCK *) FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
-
-		FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
-
-		/* Turn on FCH GPP slots */
-		FchParams->FchReset.GppEnable = TRUE;
-		FchParams->Gpp.GppFunctionEnable = TRUE;
-		FchParams->Gpp.GppLinkConfig = PortA1B1C1D1;
-		FchParams->Gpp.PortCfg[0].PortPresent = TRUE;
-		FchParams->Gpp.PortCfg[1].PortPresent = TRUE;
-		FchParams->Gpp.PortCfg[2].PortPresent = TRUE;
-		FchParams->Gpp.PortCfg[3].PortPresent = TRUE;
-		FchParams->FchReset.SataEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2);
-		FchParams->FchReset.IdeEnable = (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
-
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
-
-		/* Turn on FCH GPP slots */
-		FchParams->Gpp.GppFunctionEnable = TRUE;
-		FchParams->Gpp.GppLinkConfig = PortA1B1C1D1;
-
-		/* Azalia Controller OEM Codec Table Pointer */
-		FchParams->Azalia.AzaliaPinCfg = TRUE;
-		FchParams->Azalia.AzaliaConfig = (const AZALIA_PIN){
-			.AzaliaSdin0 = (CONFIG_AZ_PIN >> 0) & 0x03,
-			.AzaliaSdin1 = (CONFIG_AZ_PIN >> 2) & 0x03,
-			.AzaliaSdin2 = (CONFIG_AZ_PIN >> 4) & 0x03,
-			.AzaliaSdin3 = (CONFIG_AZ_PIN >> 6) & 0x03
-		};
-		FchParams->Azalia.AzaliaOemCodecTablePtr = CodecTableList;
-		/* Azalia Controller Front Panel OEM Table Pointer */
-
-		/* Fan Control */
-		oem_fan_control(FchParams);
-	}
-	printk(BIOS_DEBUG, "Done\n");
-
-	return AGESA_SUCCESS;
-}
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig
deleted file mode 100644
index c8565341d7..0000000000
--- a/src/mainboard/amd/lamar/Kconfig
+++ /dev/null
@@ -1,82 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config BOARD_AMD_LAMAR
-	def_bool n
-
-if BOARD_AMD_LAMAR
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	#select BINARYPI_LEGACY_WRAPPER
-	#select ROMCC_BOOTBLOCK
-	select CPU_AMD_PI_00630F01
-	select NORTHBRIDGE_AMD_PI_00630F01
-	select SOUTHBRIDGE_AMD_PI_BOLTON
-	select DEFAULT_POST_ON_LPC
-	select SUPERIO_FINTEK_F81216H
-	select HAVE_OPTION_TABLE
-	select HAVE_PIRQ_TABLE
-	select HAVE_MP_TABLE
-	select HAVE_ACPI_TABLES
-	select BOARD_ROMSIZE_KB_8192
-	select GFXUMA
-
-config MAINBOARD_DIR
-	string
-	default "amd/lamar"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "DB-FP3"
-
-config MAINBOARD_SERIAL_NUMBER
-	string
-	default "52198A"
-
-config MAX_CPUS
-	int
-	default 4
-
-config IRQ_SLOT_COUNT
-	int
-	default 11
-
-config ONBOARD_VGA_IS_PRIMARY
-	bool
-	default y
-
-config HUDSON_XHCI_FWM_FILE
-	string
-	default "3rdparty/blobs/southbridge/amd/bolton/xhci.bin"
-
-config AZ_PIN
-	hex
-	default 0x02
-
-config ENABLE_DP3_DAUGHTER_CARD_IN_J120
-	bool "Use J120 as an additional graphics port"
-	default n
-	help
-	  The PCI Express slot at J120 can be configured as an additional
-	  DisplayPort connector using an adapter card from AMD or as a normal
-	  PCI Express (x4) slot.
-
-	  By default, the connector is configured as a PCI Express (x4) slot.
-
-	  Select this option to enable the slot for use with one of AMD's
-	  passive graphics port expander cards (only available from AMD).
-
-endif # BOARD_AMD_LAMAR
diff --git a/src/mainboard/amd/lamar/Kconfig.name b/src/mainboard/amd/lamar/Kconfig.name
deleted file mode 100644
index 75eec04ae3..0000000000
--- a/src/mainboard/amd/lamar/Kconfig.name
+++ /dev/null
@@ -1,3 +0,0 @@
-# Disabled
-#config BOARD_AMD_LAMAR
-#	bool "Lamar"
diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc
deleted file mode 100644
index 37c1dceead..0000000000
--- a/src/mainboard/amd/lamar/Makefile.inc
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += BiosCallOuts.c
-romstage-y += OemCustomize.c
-
-ramstage-y += BiosCallOuts.c
-ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/lamar/OemCustomize.c b/src/mainboard/amd/lamar/OemCustomize.c
deleted file mode 100644
index 4c1832b154..0000000000
--- a/src/mainboard/amd/lamar/OemCustomize.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012        Advanced Micro Devices, Inc.
- *               2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <AGESA.h>
-
-
-static const PCIe_PORT_DESCRIPTOR PortList[] = {
-
-	/*
-	 * Lanes to pins to PCI device mapping can be found in section 2.12 of the
-	 * BIOS and Kernel Developer's Guide for AMD Family 15h Models 30h-3Fh
-	 */
-
-	{	/* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 31),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortEnabled,
-				ChannelTypeExt6db, 0, 0,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled,
-				175,
-				0
-		)
-	},
-
-	{	/* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 11),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortEnabled,
-				ChannelTypeExt6db, 0, 0,
-				HotplugDisabled,
-				PcieGenMaxSupported,
-				PcieGenMaxSupported,
-				AspmDisabled,
-				176,
-				0
-		)
-	},
-
-	{	/* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(
-				CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine,
-				12, 15
-		),
-		PCIE_PORT_DATA_INITIALIZER_V2(
-				PortEnabled,
-				ChannelTypeExt6db, 0, 0,
-				HotplugDisabled,
-				PcieGenMaxSupported, PcieGenMaxSupported,
-				AspmDisabled,
-				177,
-				0
-		)
-	},
-
-};
-
-static const PCIe_DDI_DESCRIPTOR DdiList[] = {
-	{	/* DP3 */
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(
-				CONFIG(ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine,
-				12, 15
-		),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux4, Hdp4)
-	},
-
-	{	/* DP2 */
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 36, 39),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3)
-	},
-
-	{	/* DP1 */
-		0,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2)
-	},
-
-	{	/* DP0 */
-		DESCRIPTOR_TERMINATE_LIST,
-		PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 4, 7),
-		PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1)
-	},
-};
-
-static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
-	.Flags        = DESCRIPTOR_TERMINATE_LIST,
-	.SocketId     = 0,
-	.PciePortList = PortList,
-	.DdiLinkList  = DdiList
-};
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID
-OemCustomizeInitEarly (
-	IN  OUT AMD_EARLY_PARAMS    *InitEarly
-	)
-{
-	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
-}
diff --git a/src/mainboard/amd/lamar/acpi/gpe.asl b/src/mainboard/amd/lamar/acpi/gpe.asl
deleted file mode 100644
index 297d9b47cb..0000000000
--- a/src/mainboard/amd/lamar/acpi/gpe.asl
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Scope(\_GPE) {	/* Start Scope GPE */
-
-	/*  General event 3  */
-	Method(_L03) {
-		/* DBGO("\\_GPE\\_L00\n") */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Legacy PM event  */
-	Method(_L08) {
-		/* DBGO("\\_GPE\\_L08\n") */
-	}
-
-	/*  Temp warning (TWarn) event  */
-	Method(_L09) {
-		/* DBGO("\\_GPE\\_L09\n") */
-		/* Notify (\_TZ.TZ00, 0x80) */
-	}
-
-	/*  USB controller PME#  */
-	Method(_L0B) {
-		/* DBGO("\\_GPE\\_L0B\n") */
-		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  ExtEvent0 SCI event  */
-	Method(_L10) {
-		/* DBGO("\\_GPE\\_L10\n") */
-	}
-
-
-	/*  ExtEvent1 SCI event  */
-	Method(_L11) {
-		/* DBGO("\\_GPE\\_L11\n") */
-	}
-
-	/*  GPIO0 or GEvent8 event  */
-	Method(_L18) {
-		/* DBGO("\\_GPE\\_L18\n") */
-		Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PCI0.PBR3, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-
-	/*  Azalia SCI event  */
-	Method(_L1B) {
-		/* DBGO("\\_GPE\\_L1B\n") */
-		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
-		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
-	}
-}	/* End Scope GPE */
diff --git a/src/mainboard/amd/lamar/acpi/mainboard.asl b/src/mainboard/amd/lamar/acpi/mainboard.asl
deleted file mode 100644
index d251657e0b..0000000000
--- a/src/mainboard/amd/lamar/acpi/mainboard.asl
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-	/* Data to be patched by the BIOS during POST */
-	/* FIXME the patching is not done yet! */
-	/* Memory related values */
-	Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
-	Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
-	Name(PBLN, 0x0)	/* Length of BIOS area */
-
-	Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
-	Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
-	Name(HPBA, 0xFED00000)	/* Base address of HPET table */
-
-	/* Some global data */
-	Name(OSVR, 3)   /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
-	Name(OSV, Ones) /* Assume nothing */
-	Name(PMOD, One) /* Assume APIC */
-
-	/* AcpiGpe0Blk */
-	OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)
-		Field(GP0B, ByteAcc, NoLock, Preserve) {
-		, 11,
-		USBS, 1,
-	}
diff --git a/src/mainboard/amd/lamar/acpi/routing.asl b/src/mainboard/amd/lamar/acpi/routing.asl
deleted file mode 100644
index 531ceeae48..0000000000
--- a/src/mainboard/amd/lamar/acpi/routing.asl
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012        Advanced Micro Devices, Inc.
- *               2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-	/* Routing is in System Bus scope */
-	Name(PR0, Package(){
-		/* NB devices */
-		/* Bus 0, Dev 0 - F15 Host Controller */
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, INTB, 0 },
-		Package(){0x0001FFFF, 1, INTC, 0 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, INTC, 0 },
-		Package(){0x0002FFFF, 1, INTD, 0 },
-		Package(){0x0002FFFF, 2, INTA, 0 },
-		Package(){0x0002FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, INTD, 0 },
-		Package(){0x0003FFFF, 1, INTA, 0 },
-		Package(){0x0003FFFF, 2, INTB, 0 },
-		Package(){0x0003FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, INTA, 0 },
-		Package(){0x0004FFFF, 1, INTB, 0 },
-		Package(){0x0004FFFF, 2, INTC, 0 },
-		Package(){0x0004FFFF, 3, INTD, 0 },
-
-		/* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
-		Package(){0x0005FFFF, 0, INTB, 0 },
-		Package(){0x0005FFFF, 1, INTC, 0 },
-		Package(){0x0005FFFF, 2, INTD, 0 },
-		Package(){0x0005FFFF, 3, INTA, 0 },
-
-		/* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
-		Package(){0x0006FFFF, 0, INTC, 0 },
-		Package(){0x0006FFFF, 1, INTD, 0 },
-		Package(){0x0006FFFF, 2, INTA, 0 },
-		Package(){0x0006FFFF, 3, INTB, 0 },
-
-		/* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
-		Package(){0x0007FFFF, 0, INTD, 0 },
-		Package(){0x0007FFFF, 1, INTA, 0 },
-		Package(){0x0007FFFF, 2, INTB, 0 },
-		Package(){0x0007FFFF, 3, INTC, 0 },
-
-		/* Bus 0, Dev 8 - Southbridge port (normally hidden) */
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
-		Package(){0x0014FFFF, 0, INTA, 0 },
-		Package(){0x0014FFFF, 1, INTB, 0 },
-		Package(){0x0014FFFF, 2, INTC, 0 },
-		Package(){0x0014FFFF, 3, INTD, 0 },
-
-		/* SB devices */
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, INTC, 0 },
-		Package(){0x0012FFFF, 1, INTB, 0 },
-
-		Package(){0x0013FFFF, 0, INTC, 0 },
-		Package(){0x0013FFFF, 1, INTB, 0 },
-
-		Package(){0x0016FFFF, 0, INTC, 0 },
-		Package(){0x0016FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, INTC, 0 },
-		Package(){0x0010FFFF, 1, INTB, 0 },
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, INTD, 0 },
-
-		/* Bus 0, Dev 21 Pcie Bridge */
-		Package(){0x0015FFFF, 0, INTA, 0 },
-		Package(){0x0015FFFF, 1, INTB, 0 },
-		Package(){0x0015FFFF, 2, INTC, 0 },
-		Package(){0x0015FFFF, 3, INTD, 0 },
-	})
-
-	Name(APR0, Package(){
-		/* NB devices in APIC mode */
-		/* Bus 0, Dev 0 - F15 Host Controller */
-
-		/* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
-		Package(){0x0001FFFF, 0, 0, 17 },
-		Package(){0x0001FFFF, 1, 0, 18 },
-
-		/* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */
-		Package(){0x0002FFFF, 0, 0, 18 },
-		Package(){0x0002FFFF, 1, 0, 19 },
-		Package(){0x0002FFFF, 2, 0, 16 },
-		Package(){0x0002FFFF, 3, 0, 17 },
-
-		/* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
-		Package(){0x0003FFFF, 0, 0, 19 },
-		Package(){0x0003FFFF, 1, 0, 16 },
-		Package(){0x0003FFFF, 2, 0, 17 },
-		Package(){0x0003FFFF, 3, 0, 18 },
-
-		/* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */
-		Package(){0x0004FFFF, 0, 0, 16 },
-		Package(){0x0004FFFF, 1, 0, 17 },
-		Package(){0x0004FFFF, 2, 0, 18 },
-		Package(){0x0004FFFF, 3, 0, 19 },
-
-		/* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
-		Package(){0x0014FFFF, 0, 0, 16 },
-		Package(){0x0014FFFF, 1, 0, 17 },
-		Package(){0x0014FFFF, 2, 0, 18 },
-		Package(){0x0014FFFF, 3, 0, 19 },
-
-		/* SB devices in APIC mode */
-		/* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
-		 *                            EHCI @ func 2 */
-		Package(){0x0012FFFF, 0, 0, 18 },
-		Package(){0x0012FFFF, 1, 0, 17 },
-
-		Package(){0x0013FFFF, 0, 0, 18 },
-		Package(){0x0013FFFF, 1, 0, 17 },
-
-		Package(){0x0016FFFF, 0, 0, 18 },
-		Package(){0x0016FFFF, 1, 0, 17 },
-
-		/* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
-		Package(){0x0010FFFF, 0, 0, 0x12},
-		Package(){0x0010FFFF, 1, 0, 0x11},
-
-		/* Bus 0, Dev 17 - SATA controller */
-		Package(){0x0011FFFF, 0, 0, 19 },
-
-		/* Bus0, Dev 21 PCIE Bridge */
-		Package(){0x0015FFFF, 0, 0, 16 },
-		Package(){0x0015FFFF, 1, 0, 17 },
-		Package(){0x0015FFFF, 2, 0, 18 },
-		Package(){0x0015FFFF, 3, 0, 19 },
-	})
-
-	Name(PS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS2, Package(){
-		/* The external GFX - Hooked to PCIe slot 2 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APS3, Package(){
-		/* PCIe slot - Hooked to PCIe slot 4 */
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APS5, Package(){
-		/* PCIe slot - Hooked to PCIe slot 5 */
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APS6, Package(){
-		/* PCIe slot - Hooked to PCIe slot 6 */
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PS7, Package(){
-		/* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APS7, Package(){
-		/* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	Name(PE0, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 0*/
-		Package(){0x0000FFFF, 0, INTA, 0 },
-		Package(){0x0000FFFF, 1, INTB, 0 },
-		Package(){0x0000FFFF, 2, INTC, 0 },
-		Package(){0x0000FFFF, 3, INTD, 0 },
-	})
-	Name(APE0, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 0*/
-		Package(){0x0000FFFF, 0, 0, 16 },
-		Package(){0x0000FFFF, 1, 0, 17 },
-		Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
-	})
-
-	Name(PE1, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 1*/
-		Package(){0x0000FFFF, 0, INTB, 0 },
-		Package(){0x0000FFFF, 1, INTC, 0 },
-		Package(){0x0000FFFF, 2, INTD, 0 },
-		Package(){0x0000FFFF, 3, INTA, 0 },
-	})
-	Name(APE1, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 1*/
-		Package(){0x0000FFFF, 0, 0, 17 },
-		Package(){0x0000FFFF, 1, 0, 18 },
-		Package(){0x0000FFFF, 2, 0, 19 },
-		Package(){0x0000FFFF, 3, 0, 16 },
-	})
-
-	Name(PE2, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 2*/
-		Package(){0x0000FFFF, 0, INTC, 0 },
-		Package(){0x0000FFFF, 1, INTD, 0 },
-		Package(){0x0000FFFF, 2, INTA, 0 },
-		Package(){0x0000FFFF, 3, INTB, 0 },
-	})
-	Name(APE2, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 2*/
-		Package(){0x0000FFFF, 0, 0, 18 },
-		Package(){0x0000FFFF, 1, 0, 19 },
-		Package(){0x0000FFFF, 2, 0, 16 },
-		Package(){0x0000FFFF, 3, 0, 17 },
-	})
-
-	Name(PE3, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 3 */
-		Package(){0x0000FFFF, 0, INTD, 0 },
-		Package(){0x0000FFFF, 1, INTA, 0 },
-		Package(){0x0000FFFF, 2, INTB, 0 },
-		Package(){0x0000FFFF, 3, INTC, 0 },
-	})
-	Name(APE3, Package(){
-		/* PCIe slot - Hooked to PCIe Bridge 3*/
-		Package(){0x0000FFFF, 0, 0, 19 },
-		Package(){0x0000FFFF, 1, 0, 16 },
-		Package(){0x0000FFFF, 2, 0, 17 },
-		Package(){0x0000FFFF, 3, 0, 18 },
-	})
-
-	/* SB PCI Bridge J21, J22 */
-	Name(PCIB, Package(){
-		/* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */
-		Package(){0x0005FFFF, 0, 0, 0x14 },
-		Package(){0x0005FFFF, 1, 0, 0x15 },
-		Package(){0x0005FFFF, 2, 0, 0x16 },
-		Package(){0x0005FFFF, 3, 0, 0x17 },
-
-		Package(){0x0006FFFF, 0, 0, 0x15 },
-		Package(){0x0006FFFF, 1, 0, 0x16 },
-		Package(){0x0006FFFF, 2, 0, 0x17 },
-		Package(){0x0006FFFF, 3, 0, 0x14 },
-	})
diff --git a/src/mainboard/amd/lamar/acpi/si.asl b/src/mainboard/amd/lamar/acpi/si.asl
deleted file mode 100644
index bec166c72b..0000000000
--- a/src/mainboard/amd/lamar/acpi/si.asl
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-	Scope(\_SI) {
-		Method(_SST, 1) {
-			/* DBGO("\\_SI\\_SST\n") */
-			/* DBGO("   New Indicator state: ") */
-			/* DBGO(Arg0) */
-			/* DBGO("\n") */
-		}
-	} /* End Scope SI */
diff --git a/src/mainboard/amd/lamar/acpi/sleep.asl b/src/mainboard/amd/lamar/acpi/sleep.asl
deleted file mode 100644
index f7edfb9119..0000000000
--- a/src/mainboard/amd/lamar/acpi/sleep.asl
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Wake status package */
-Name(WKST,Package(){Zero, Zero})
-
-/*
-* \_PTS - Prepare to Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2, etc
-*
-* Exit:
-*		-none-
-*
-* The _PTS control method is executed at the beginning of the sleep process
-* for S1-S5. The sleeping value is passed to the _PTS control method.  This
-* control method may be executed a relatively long time before entering the
-* sleep state and the OS may abort the operation without notification to
-* the ACPI driver.  This method cannot modify the configuration or power
-* state of any device in the system.
-*/
-Method(\_PTS, 1) {
-	/* DBGO("\\_PTS\n") */
-	/* DBGO("From S0 to S") */
-	/* DBGO(Arg0) */
-	/* DBGO("\n") */
-
-	/* Clear sleep SMI status flag and enable sleep SMI trap. */
-	/*Store(One, CSSM)
-	Store(One, SSEN)*/
-
-	/* On older chips, clear PciExpWakeDisEn */
-	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-	*	Store(0,\_SB.PWDE)
-	*}
-	*/
-
-	/* Clear wake status structure. */
-	Store(0, Index(WKST,0))
-	Store(0, Index(WKST,1))
-
-	Store (0x07, UPWS)
-} /* End Method(\_PTS) */
-
-/*
-*	\_BFS OEM Back From Sleep method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		-none-
-*/
-Method(\_BFS, 1) {
-	/* DBGO("\\_BFS\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-}
-
-/*
-*  \_WAK System Wake method
-*
-*	Entry:
-*		Arg0=The value of the sleeping state S1=1, S2=2
-*
-*	Exit:
-*		Return package of 2 DWords
-*		Dword 1 - Status
-*			0x00000000	wake succeeded
-*			0x00000001	Wake was signaled but failed due to lack of power
-*			0x00000002	Wake was signaled but failed due to thermal condition
-*		Dword 2 - Power Supply state
-*			if non-zero the effective S-state the power supply entered
-*/
-Method(\_WAK, 1) {
-	/* DBGO("\\_WAK\n") */
-	/* DBGO("From S") */
-	/* DBGO(Arg0) */
-	/* DBGO(" to S0\n") */
-
-	/* Re-enable HPET */
-	Store(1,USBS)
-
-	Return(WKST)
-} /* End Method(\_WAK) */
diff --git a/src/mainboard/amd/lamar/acpi/thermal.asl b/src/mainboard/amd/lamar/acpi/thermal.asl
deleted file mode 100644
index 73077ac4d3..0000000000
--- a/src/mainboard/amd/lamar/acpi/thermal.asl
+++ /dev/null
@@ -1,2 +0,0 @@
-/* No license required */
-/* No thermal zone functionality */
diff --git a/src/mainboard/amd/lamar/acpi/usb_oc.asl b/src/mainboard/amd/lamar/acpi/usb_oc.asl
deleted file mode 100644
index 4254e7e469..0000000000
--- a/src/mainboard/amd/lamar/acpi/usb_oc.asl
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012        Advanced Micro Devices, Inc.
- * Copyright (C) 2013 - 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* USB overcurrent mapping pins.   */
-Name(UOM0, 0)
-Name(UOM1, 2)
-Name(UOM2, 0)
-Name(UOM3, 7)
-Name(UOM4, 2)
-Name(UOM5, 2)
-Name(UOM6, 6)
-Name(UOM7, 2)
-Name(UOM8, 6)
-Name(UOM9, 6)
diff --git a/src/mainboard/amd/lamar/acpi_tables.c b/src/mainboard/amd/lamar/acpi_tables.c
deleted file mode 100644
index 65e74baf40..0000000000
--- a/src/mainboard/amd/lamar/acpi_tables.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* create all subtables for processors */
-	current = acpi_create_madt_lapics(current);
-
-	/* Write southbridge IOAPIC, only one */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
-					   IO_APIC_ADDR, 0);
-
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS+1,
-					   0xFEC20000, 24);
-
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-						current, 0, 9, 9, 0xF);
-	/* 0: mean bus 0--->ISA */
-	/* 0: PIC 0 */
-	/* 2: APIC 2 */
-	/* 5 mean: 0101 --> Edge-triggered, Active high */
-
-	/* create all subtables for processors */
-	current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
-	/* 1: LINT1 connect to NMI */
-
-	return current;
-}
diff --git a/src/mainboard/amd/lamar/board_info.txt b/src/mainboard/amd/lamar/board_info.txt
deleted file mode 100644
index 8bce92e85c..0000000000
--- a/src/mainboard/amd/lamar/board_info.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-Board name: DB-FP3 (Lamar)
-Category: eval
-ROM package: SOIC-8
-ROM protocol: SPI
-ROM socketed: n
diff --git a/src/mainboard/amd/lamar/cmos.layout b/src/mainboard/amd/lamar/cmos.layout
deleted file mode 100644
index dc9b789385..0000000000
--- a/src/mainboard/amd/lamar/cmos.layout
+++ /dev/null
@@ -1,59 +0,0 @@
-#*****************************************************************************
-#
-#  This file is part of the coreboot project.
-#
-#  Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-#  This program is free software; you can redistribute it and/or modify
-#  it under the terms of the GNU General Public License as published by
-#  the Free Software Foundation; version 2 of the License.
-#
-#  This program is distributed in the hope that it will be useful,
-#  but WITHOUT ANY WARRANTY; without even the implied warranty of
-#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#  GNU General Public License for more details.
-#*****************************************************************************
-
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-444          1       e       1        nmi
-728        256       h       0        user_data
-984         16       h       0        check_sum
-# Reserve the extended AMD configuration registers
-1000        24       r       0        amd_reserved
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-8     0     400Mhz
-8     1     333Mhz
-8     2     266Mhz
-8     3     200Mhz
-9     0     off
-9     1     87.5%
-9     2     75.0%
-9     3     62.5%
-9     4     50.0%
-9     5     37.5%
-9     6     25.0%
-9     7     12.5%
-
-checksums
-
-checksum 392 983 984
diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb
deleted file mode 100644
index 5c88a3c557..0000000000
--- a/src/mainboard/amd/lamar/devicetree.cb
+++ /dev/null
@@ -1,101 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012        Advanced Micro Devices, Inc.
-#               2013 - 2014 Sage Electronic Engineering, LLC
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/amd/pi/00630F01/root_complex
-	device cpu_cluster 0 on
-		chip cpu/amd/pi/00630F01
-		  device lapic 10 on end
-		end
-	end
-
-	device domain 0 on
-		subsystemid 0x1022 0x1410 inherit
-
-		chip northbridge/amd/pi/00630F01
-			device pci 0.0 on end   # 0x1422 Root Complex
-			device pci 0.2 off end  # 0x1423 IOMMU
-			device pci 1.0 on end   # 0x13XX Internal Graphics
-			device pci 1.1 on end   # 0x1308 DisplayPort/HDMI Audio
-			device pci 2.0 on end   # 0x1424 GFX PCIe Host Bridge
-			device pci 2.1 on end   # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119)
-			device pci 2.2 off end  # 0x1425 P2P Bridge for GFX PCIe Port 1
-			device pci 3.0 on end   # 0x1424 GPP PCIe Host Bridge
-			device pci 3.1 on end   # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118)
-			device pci 3.2 on end   # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120)
-			device pci 3.3 off end  # 0x1426 P2P Bridge for GPP PCIe Port 2
-			device pci 3.4 off end  # 0x1426 P2P Bridge for GPP PCIe Port 3
-			device pci 3.5 off end  # 0x1426 P2P Bridge for GPP PCIe Port 4
-			device pci 4.0 on end   # 0x1424 UMI PCIe Host Bridge
-#				device pci 4.1 on end   # 0x1426 P2P bridge for UMI link
-#				device pci 4.2 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 3
-#				device pci 4.3 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 2
-#				device pci 4.4 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 1
-#				device pci 4.5 off end  # 0x1426 Virtual P2P bridge for SB PCIe Port 0
-		end	#chip northbridge/amd/pi/00630F01
-
-		chip southbridge/amd/pi/hudson
-			device pci 10.0 on end  # 0x7814 XHCI HC0
-			device pci 10.1 on end  # 0x7814 XHCI HC1
-			device pci 11.0 on end  # 0x7800-0x7805 SATA (device ID depends on mode)
-			device pci 12.0 on end  # 0x7807 USB OHCI
-			device pci 12.2 on end  # 0x7808 USB EHCI
-			device pci 13.0 on end  # 0x7807 USB OHCI
-			device pci 13.2 on end  # 0x7808 USB EHCI
-			device pci 14.0 on end  # SM
-			device pci 14.1 on end  # 0x780C IDE
-			device pci 14.2 on end  # 0x780D HDA
-			device pci 14.3 on      # 0x780E LPC
-				chip superio/fintek/f81216h
-					register "conf_key_mode" = "0x77"
-					device pnp 4e.0 on			# COM1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 4e.1 on			# COM2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 4e.2 off end		# COM3
-					device pnp 4e.3 off end		# COM4
-					device pnp 4e.8 off end		# WDT
-				end # f81865f
-			end #LPC
-			device pci 14.4 on end  # 0x780F PCI :: PCI-b conflict with GPIO.
-			device pci 14.5 on end  # 0x7809 USB OHCI
-			device pci 14.7 on end  # 0x7806 SD Flash Controller
-			device pci 15.0 on end  # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller)
-			device pci 15.1 on end  # 0x43A1 SB GPP Port 1 (mPCIe slot J122)
-			device pci 15.2 on end  # 0x43A2 SB GPP Port 2 (mPCIe slot J123)
-			device pci 15.3 off end # 0x43A3 SB GPP Port 3
-				register "gpp_configuration" = "4"
-			device pci 16.0 on end  # 0x7809 USB OHCI (when the xHCI device is disabled)
-		end	#southbridge/amd/pi/hudson
-
-		chip northbridge/amd/pi/00630F01
-			device pci 18.0 on end # 0x141A HT Configuration
-			device pci 18.1 on end # 0x141B Address Maps
-			device pci 18.2 on end # 0x141C DRAM Configuration
-			device pci 18.3 on end # 0x141D Miscellaneous
-			device pci 18.4 on end # 0x141E Power Management
-			device pci 18.5 on end # 0x141F Northbridge
-
-			register "spdAddrLookup" = "
-			{
-				{ {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
-			}"
-		end
-
-	end #domain
-end #northbridge/amd/pi/00630F01/root_complex
diff --git a/src/mainboard/amd/lamar/dsdt.asl b/src/mainboard/amd/lamar/dsdt.asl
deleted file mode 100644
index 1db743d5ca..0000000000
--- a/src/mainboard/amd/lamar/dsdt.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012         Advanced Micro Devices, Inc.
- * Copyright (C) 2013 - 2014  Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* DefinitionBlock Statement */
-#include <arch/acpi.h>
-DefinitionBlock (
-	"DSDT.AML",	/* Output filename */
-	"DSDT",		/* Signature */
-	0x02,		/* DSDT Revision, needs to be 2 for 64bit */
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x00010001	/* OEM Revision */
-	)
-{	/* Start of ASL file */
-	/* #include <arch/x86/acpi/debug.asl> */	/* Include global debug methods if needed */
-
-	/* Globals for the platform */
-	#include "acpi/mainboard.asl"
-
-	/* Describe the USB Overcurrent pins */
-	#include "acpi/usb_oc.asl"
-
-	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
-
-	/* Describe the processor tree (\_PR) */
-	#include <cpu/amd/pi/00630F01/acpi/cpu.asl>
-
-	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/common/acpi/sleepstates.asl>
-
-	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
-	#include "acpi/sleep.asl"
-
-	/* System Bus */
-	Scope(\_SB) { /* Start \_SB scope */
-		/* global utility methods expected within the \_SB scope */
-		#include <arch/x86/acpi/globutil.asl>
-
-		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
-		#include "acpi/routing.asl"
-
-		Device(PWRB) {
-			Name(_HID, EISAID("PNP0C0C"))
-			Name(_UID, 0xAA)
-			Name(_PRW, Package () {3, 0x04})
-			Name(_STA, 0x0B)
-		}
-
-		Device(PCI0) {
-			/* Describe the AMD Northbridge */
-			#include <northbridge/amd/pi/00630F01/acpi/northbridge.asl>
-
-			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
-		}
-
-		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
-
-	} /* End \_SB scope */
-
-	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
-
-	/* Define the General Purpose Events for the platform */
-	#include "acpi/gpe.asl"
-
-	/* Define the Thermal zones and methods for the platform */
-	#include "acpi/thermal.asl"
-
-	/* Define the System Indicators for the platform */
-	#include "acpi/si.asl"
-}
-/* End of ASL file */
diff --git a/src/mainboard/amd/lamar/irq_tables.c b/src/mainboard/amd/lamar/irq_tables.c
deleted file mode 100644
index fc3fbec2d4..0000000000
--- a/src/mainboard/amd/lamar/irq_tables.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-
-static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
-			    u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
-			    u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
-			    u8 slot, u8 rfu)
-{
-	pirq_info->bus = bus;
-	pirq_info->devfn = devfn;
-	pirq_info->irq[0].link = link0;
-	pirq_info->irq[0].bitmap = bitmap0;
-	pirq_info->irq[1].link = link1;
-	pirq_info->irq[1].bitmap = bitmap1;
-	pirq_info->irq[2].link = link2;
-	pirq_info->irq[2].bitmap = bitmap2;
-	pirq_info->irq[3].link = link3;
-	pirq_info->irq[3].bitmap = bitmap3;
-	pirq_info->slot = slot;
-	pirq_info->rfu = rfu;
-}
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	u32 slot_num;
-	u8 *v;
-
-	u8 sum = 0;
-	int i;
-
-	/* Align the table to be 16 byte aligned. */
-	addr += 15;
-	addr &= ~15;
-
-	/* This table must be between 0xf0000 & 0x100000 */
-	printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
-
-	pirq = (void *)(addr);
-	v = (u8 *) (addr);
-
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version = PIRQ_VERSION;
-
-	pirq->rtr_bus = 0;
-	pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
-
-	pirq->exclusive_irqs = 0;
-
-	pirq->rtr_vendor = 0x1002;
-	pirq->rtr_device = 0x4384;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *)(&pirq->checksum + 1);
-	slot_num = 0;
-
-	/* pci bridge */
-	write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
-			0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
-			0);
-	pirq_info++;
-
-	slot_num++;
-
-	pirq->size = 32 + 16 * slot_num;
-
-	for (i = 0; i < pirq->size; i++)
-		sum += v[i];
-
-	sum = pirq->checksum - sum;
-
-	if (sum != pirq->checksum) {
-		pirq->checksum = sum;
-	}
-
-	printk(BIOS_INFO, "%s done.\n", __func__);
-
-	return (unsigned long)pirq_info;
-}
diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c
deleted file mode 100644
index 264c603357..0000000000
--- a/src/mainboard/amd/lamar/mainboard.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/pi/00630F01/pci_devs.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <southbridge/amd/pi/hudson/pci_devs.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-
-/***********************************************************
- * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
- * This table is responsible for physically routing the PIC and
- * IOAPIC IRQs to the different PCI devices on the system.  It
- * is read and written via registers 0xC00/0xC01 as an
- * Index/Data pair.  These values are chipset and mainboard
- * dependent and should be updated accordingly.
- *
- * These values are used by the PCI configuration space,
- * MP Tables.  TODO: Make ACPI use these values too.
- */
-static const u8 mainboard_picr_data[] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
-	[0x10] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,
-	[0x18] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x28] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/22 INTA-C */
-	[0x30] = 0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x1F,
-	[0x38] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* [40..41] IDE, SATA */
-	[0x40] = 0x1F,0x0F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x48] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* [50..53] GPPInt0 - 3 */
-	[0x50] = 0x0A,0x0B,0x0A,0x0B,
-	[0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x60] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* [80..81] Northbridge devices (indices above C00/C01 range) */
-	[0x80] = 0x0C,0x1F,
-};
-
-static const u8 mainboard_intr_data[] = {
-	/* INTA# - INTH# */
-	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
-	/* Misc-nil,0,1,2, INT from Serial irq */
-	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
-	/* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
-	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
-	[0x18] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* IMC INT0 - 5 */
-	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x28] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* USB Devs 18/19/20/22 INTA-C */
-	[0x30] = 0x11,0x12,0x11,0x12,0x11,0x12,0x11,0x1F,
-	[0x38] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* SATA */
-	[0x40] = 0x11,0x13,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x48] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* [50..53] GPPInt0 - 3 */
-	[0x50] = 0x10,0x11,0x12,0x13,
-	[0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x60] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x70] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
-	/* [80..81] Northbridge devices (indices above C00/C01 range) */
-	[0x80] = 0x17,0x10,
-};
-
-/*
- * This table defines the index into the picr/intr_data
- * tables for each device.  Any enabled device and slot
- * that uses hardware interrupts should have an entry
- * in this table to define its index into the FCH
- * PCI_INTR register 0xC00/0xC01.  This index will define
- * the interrupt that it should use.  Putting PIRQ_A into
- * the PIN A index for a device will tell that device to
- * use PIC IRQ 10 if it uses PIN A for its hardware INT.
- */
-static const struct pirq_struct mainboard_pirq_data[] = {
-	{NB_PCIE_PORT1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* PCIe J119:  02.1 */
-	{NB_PCIE_PORT3_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* PCIe J118:  03.1 */
-	{NB_PCIE_PORT4_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* PCIe J120:  03.2 */
-	{XHCI_DEVFN,	{PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* XHCI:       10.0 */
-	{XHCI2_DEVFN,	{PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}},	/* XHCI:       10.1 */
-	{SATA_DEVFN,	{PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SATA:       11.0 */
-	{OHCI1_DEVFN,	{PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI1:      12.0 */
-	{EHCI1_DEVFN,	{PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},	/* EHCI1:      12.2 */
-	{OHCI2_DEVFN,	{PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI2:      13.0 */
-	{EHCI2_DEVFN,	{PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},	/* EHCI2:      13.2 */
-	{SMBUS_DEVFN,	{PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* SMBUS:      14.0 */
-	{IDE_DEVFN,		{PIRQ_NC, PIRQ_IDE, PIRQ_NC, PIRQ_NC}},		/* IDE:        14.1 */
-	{HDA_DEVFN,		{PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* HDA:        14.2 */
-	{SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}},		/* PCI:        14.4 */
-	{OHCI4_DEVFN,	{PIRQ_NC, PIRQ_NC, PIRQ_OHCI4, PIRQ_NC}},	/* OHCI4:      14.5 */
-	{SD_DEVFN,		{PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}},		/* SD:         14.7 */
-	{SB_PCIE_PORT1_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* LAN:        15.0 */
-	{SB_PCIE_PORT2_DEVFN,	{PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},	/* mPCIe J122: 15.1 */
-	{SB_PCIE_PORT3_DEVFN,	{PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},	/* mPCIe J123: 15.2 */
-	{SB_PCIE_PORT4_DEVFN,	{PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},	/* unused      15.3 */
-	{OHCI3_DEVFN,	{PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}},	/* OHCI3:      16.0 (same device as xHCI 10.0) */
-	{EHCI3_DEVFN,	{PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}},	/* EHCI3:      16.2 (same device as xHCI 10.1) */
-};
-
-/* PIRQ Setup */
-static void pirq_setup(void)
-{
-	pirq_data_ptr = mainboard_pirq_data;
-	pirq_data_size = FCH_INT_TABLE_SIZE /* FIXME sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct) */;
-	intr_data_ptr = mainboard_intr_data;
-	picr_data_ptr = mainboard_picr_data;
-}
-
-/*************************************************
- * enable the dedicated function in lamar board.
- *************************************************/
-static void mainboard_enable(struct device *dev)
-{
-	printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
-
-	/* Initialize the PIRQ data structures for consumption */
-	pirq_setup();
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c
deleted file mode 100644
index 1f2093dd3a..0000000000
--- a/src/mainboard/amd/lamar/mptable.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/smp/mpspec.h>
-#include <arch/ioapic.h>
-#include <stdint.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/common/amd_pci_util.h>
-#include <drivers/generic/ioapic/chip.h>
-#include <southbridge/amd/pi/hudson/amd_pci_int_defs.h>
-#include <northbridge/amd/pi/00630F01/pci_devs.h>
-
-#define NB_APIC_ADDR ((u8 *)0xFEC20000)
-
-#define PCI_INT(bus, dev, fn, apic, pin) \
-		if (((pin) != 0x00) && ((pin) != 0x1F)) \
-		{ \
-			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apic, (pin)); \
-		}
-
-#define IO_LOCAL_INT(type, intr, apicid, pin) \
-		smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
-
-static void *smp_write_config_table(void *v)
-{
-	struct mp_config_table *mc;
-	int bus_isa;
-
-	/* Initialize the MP_Table */
-	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-
-	mptable_init(mc, LOCAL_APIC_ADDR);
-
-	/*
-	 * Type 0: Processor Entries:
-	 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
-	 * CPU Signature (Stepping, Model, Family),
-	 * Feature Flags
-	 */
-	smp_write_processors(mc);
-
-	/*
-	 * Type 1: Bus Entries:
-	 * Bus ID, Bus Type
-	 */
-	mptable_write_buses(mc, NULL, &bus_isa);
-
-	/*
-	 * Type 2: I/O APICs:
-	 * APIC ID, Version, APIC Flags:EN, Address
-	 */
-
-	u8 apicid_nb = (io_apic_read(NB_APIC_ADDR, 0x00) >> 24);	/* Get the GNB IOAPIC ID */
-	u8 apicver_nb = (io_apic_read(NB_APIC_ADDR, 0x01) & 0xFF);	/* Get the GNB IOAPIC version */
-
-	smp_write_ioapic(mc, apicid_nb, apicver_nb, NB_APIC_ADDR);
-
-	u8 apicid_sb = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);		/* Get the southbridge IOAPIC ID */
-	u8 apicver_sb = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);	/* Get the southbridge IOAPIC version */
-
-	smp_write_ioapic(mc, apicid_sb, apicver_sb, VIO_APIC_VADDR);
-
-	/*
-	 * Type 3: I/O Interrupt Table Entries:
-	 * Int Type, Int Polarity, Int Level, Source Bus ID,
-	 * Source Bus IRQ, Dest APIC ID, Dest PIN#
-	 */
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_nb, 0);
-	mptable_add_isa_interrupts(mc, bus_isa, apicid_sb, 0);
-
-	/* PCI interrupts are level triggered, and are
-	 * associated with a specific bus/device/function tuple.
-	 */
-
-	/* APU Internal Graphic Device */
-	PCI_INT(0x0, 0x01, 0x0, apicid_nb, intr_data_ptr[PIRQ_GFX]);
-	PCI_INT(0x0, 0x01, 0x1, apicid_nb, intr_data_ptr[PIRQ_ACTL]);
-
-	/* SMBUS / ACPI */
-	PCI_INT(0x0, 0x14, 0x0, apicid_sb, intr_data_ptr[PIRQ_SMBUS]);
-
-	/* Southbridge HD Audio */
-	PCI_INT(0x0, 0x14, 0x2, apicid_sb, intr_data_ptr[PIRQ_HDA]);
-
-	/* USB */
-	PCI_INT(0x0, 0x12, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI1]);
-	PCI_INT(0x0, 0x12, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI1]);
-	PCI_INT(0x0, 0x13, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI2]);
-	PCI_INT(0x0, 0x13, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI2]);
-	PCI_INT(0x0, 0x16, 0x0, apicid_sb, intr_data_ptr[PIRQ_OHCI3]);
-	PCI_INT(0x0, 0x16, 0x2, apicid_sb, intr_data_ptr[PIRQ_EHCI3]);
-	PCI_INT(0x0, 0x14, 0x5, apicid_sb, intr_data_ptr[PIRQ_OHCI4]);
-
-	/* SATA */
-	PCI_INT(0x0, 0x11, 0x0, apicid_sb, intr_data_ptr[PIRQ_SATA]);
-
-	/* IDE */
-	PCI_INT(0x0, 0x14, 0x1, apicid_sb, intr_data_ptr[PIRQ_IDE]);
-
-	/* PCI slots */
-	/* NB Gfx PCIe Bridges */
-	PCI_INT(0, 0x2, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
-	PCI_INT(0, 0x2, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
-
-	/* NB GPP PCIe Bridges */
-	PCI_INT(0, 0x3, 0x1, apicid_nb, intr_data_ptr[PIRQ_A]);
-	PCI_INT(0, 0x3, 0x2, apicid_nb, intr_data_ptr[PIRQ_A]);
-	PCI_INT(0, 0x3, 0x3, apicid_nb, intr_data_ptr[PIRQ_A]);
-	PCI_INT(0, 0x3, 0x4, apicid_nb, intr_data_ptr[PIRQ_A]);
-	PCI_INT(0, 0x3, 0x5, apicid_nb, intr_data_ptr[PIRQ_A]);
-
-	/* PCI slots */
-	PCI_INT(0, 0x14, 0x4, apicid_sb, intr_data_ptr[PIRQ_A]);
-
-	/* FCH GPP PCIe Bridges */
-	PCI_INT(0x0, 0x15, 0x0, apicid_sb, intr_data_ptr[PIRQ_A]);
-	/* FCH PCIe PortB */
-	PCI_INT(0x0, 0x15, 0x1, apicid_sb, intr_data_ptr[PIRQ_A]);
-	/* FCH PCIe PortC */
-	PCI_INT(0x0, 0x15, 0x2, apicid_sb, intr_data_ptr[PIRQ_A]);
-	/* FCH PCIe PortD */
-	PCI_INT(0x0, 0x15, 0x3, apicid_sb, intr_data_ptr[PIRQ_A]);
-
-	/*Local Ints:	 Type	Polarity	Trigger	 Bus ID	 IRQ	APIC ID PIN# */
-	IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
-	IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
-
-	/* There is no extension information... */
-
-	/* Compute the checksums */
-	return mptable_finalize(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
-	void *v;
-	v = smp_write_floating_table(addr, 0);	/* ADDR, Enable Virtual Wire */
-	return (unsigned long)smp_write_config_table(v);
-}
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
deleted file mode 100644
index 66188bdc1c..0000000000
--- a/src/mainboard/amd/lamar/romstage.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 - 2014 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <amdblocks/acpimmio.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
-#include <console/console.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/common/amd_defs.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-#include <superio/fintek/f81216h/f81216h.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
-
-static void romstage_main_template(void)
-{
-	misc_write32(0x28, misc_read32(0x28) | (1 << 18)); /* 24Mhz */
-	misc_write32(0x40, misc_read32(0x40) & (~(1 << 2))); /* 24Mhz */
-
-	if (!cpu_init_detectedx) {
-		post_code(0x30);
-		f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);
-		post_code(0x31);
-		console_init();
-	}
-}