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| author | Greg Watson <jarrah@users.sourceforge.net> | 2003-11-09 23:29:42 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2003-11-09 23:29:42 +0000 |
| commit | e3da4d3ce8ecf4e5424931a4ceba5bd8c82840cf (patch) | |
| tree | fdd17d0856eb78a77adfb42be23a8801683bb0ba /src | |
| parent | c8ea12d672e9bbca92257448ad0c887a206beb46 (diff) | |
| download | coreboot-e3da4d3ce8ecf4e5424931a4ceba5bd8c82840cf.tar.xz | |
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
| -rw-r--r-- | src/config/Options.lb | 17 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc4xx/Config.lb | 6 |
2 files changed, 20 insertions, 3 deletions
diff --git a/src/config/Options.lb b/src/config/Options.lb index 714bb46c90..39e4bf81c0 100644 --- a/src/config/Options.lb +++ b/src/config/Options.lb @@ -172,6 +172,11 @@ define CONFIG_CHIP_CONFIGURE export used comment "Use new chip_configure method for configuring (non-pci) devices" end +define CONFIG_USE_INIT + default 0 + export never + comment "Use stage 1 initialization code" +end ############################################### # ROM image options @@ -532,6 +537,18 @@ define PCIC0_CFGDATA export used comment "PCI Configuration Data Register" end +define PNP_CFGADDR + default none + format "0x%x" + export used + comment "PNP Configuration Address Register" +end +define PNP_CFGDATA + default none + format "0x%x" + export used + comment "PNP Configuration Data Register" +end define UART0_IO_BASE default none format "0x%x" diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb index 0617c2a790..5a95024929 100644 --- a/src/cpu/ppc/ppc4xx/Config.lb +++ b/src/cpu/ppc/ppc4xx/Config.lb @@ -9,11 +9,11 @@ uses DCACHE_RAM_SIZE ## ## PPC4XX always uses cache ram for initial setup ## -option USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=1 ## Set dcache ram above linuxbios image -option DCACHE_RAM_BASE=_RAMBASE+0x100000 +default DCACHE_RAM_BASE=_RAMBASE+0x100000 ## Dcache size is 16Kb -option DCACHE_RAM_SIZE=16384 +default DCACHE_RAM_SIZE=16384 initinclude "FAMILY_INIT" cpu/ppc/ppc4xx/ppc4xx.inc initobject cache.S |