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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2019-12-16 16:39:53 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-20 17:57:17 +0000 |
| commit | e9b1e0fe8873cb3131b0dc4741e83540e0d90a31 (patch) | |
| tree | 23cb5fff46fc92a33ca9e2c78223c03b5d27a16c /src | |
| parent | 6ee5559d6a3c1ba452a53db58ec6b41d629d92b2 (diff) | |
| download | coreboot-e9b1e0fe8873cb3131b0dc4741e83540e0d90a31.tar.xz | |
soc/intel/tigerlake: Update FSP stack and heap size
Tigerlake and Jasperlake fsp requires stack size to be minimum 192 KiB
and heap size to be minimum 128 KiB.
Updating both Kconfig to meet size requirements.
Also updated required CAR region size during boot block due to increment
in stack & heap requirement by fsp
Change-Id: I38e93b5986811ff3e0a8df5f4f36af35f308cb6b
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37764
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7bb533ab71..be4e26c2cc 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -74,22 +74,22 @@ config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE - default 0x40000 + default 0x80000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x20400 + default 0x30400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). + sum of FSP-M stack requirement (192KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE hex - default 0x10000 + default 0x20000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know |