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authorJulius Werner <jwerner@chromium.org>2016-07-29 12:30:50 -0700
committerJulius Werner <jwerner@chromium.org>2016-08-27 01:16:58 +0200
commiteb131f30a3c1bf56d24b1bea2bc2a77d458843ff (patch)
tree361364317d8b5193555b7b1ce640bf2296505056 /src
parent329031fdedb332f75b2d3ce6c165bb62d9631600 (diff)
downloadcoreboot-eb131f30a3c1bf56d24b1bea2bc2a77d458843ff.tar.xz
rockchip/rk3399: Enable ramstage compression, shuffle around memlayout
Since we now have so much more room for activities in our romstage SRAM section, we can easily fit the LZMA decompressor to enable ramstage compression. Also shuffle around memlayout sections a little more to make use of unused space, and balance out leftover memory so that all sections that might need future expansion have a reasonable amount. Change-Id: I47f2d03e520fc3103ef04257b4ba7e93874b8956 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/rockchip/rk3399/Kconfig1
-rw-r--r--src/soc/rockchip/rk3399/include/soc/memlayout.ld14
2 files changed, 7 insertions, 8 deletions
diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig
index 63e343e149..1eaa87019e 100644
--- a/src/soc/rockchip/rk3399/Kconfig
+++ b/src/soc/rockchip/rk3399/Kconfig
@@ -11,7 +11,6 @@ config SOC_ROCKCHIP_RK3399
select DRIVERS_UART_8250MEM_32
select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER
- select UNCOMPRESSED_RAMSTAGE
select UART_OVERRIDE_REFCLK
if SOC_ROCKCHIP_RK3399
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index 96dd108a1c..ec12c80e5f 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -25,13 +25,13 @@ SECTIONS
FRAMEBUFFER(0x10200000, 8M)
SRAM_START(0xFF8C0000)
- BOOTBLOCK(0xFF8C2004, 31K - 4)
- PRERAM_CBMEM_CONSOLE(0xFF8C9C00, 5K)
+ PRERAM_CBMEM_CONSOLE(0xFF8C0000, 7K)
+ TIMESTAMP(0xFF8C1C00, 1K)
+ BOOTBLOCK(0xFF8C2004, 36K - 4)
PRERAM_CBFS_CACHE(0xFF8CB000, 4K)
- TTB(0xFF8CC000, 32K)
- OVERLAP_VERSTAGE_ROMSTAGE(0xFF8D4000, 75K)
- VBOOT2_WORK(0XFF8E6C00, 12K)
- TIMESTAMP(0xFF8E9C00, 1K)
- STACK(0xFF8EA000, 24K)
+ TTB(0xFF8CC000, 24K)
+ OVERLAP_VERSTAGE_ROMSTAGE(0xFF8D2000, 92K)
+ VBOOT2_WORK(0XFF8E9000, 12K)
+ STACK(0xFF8EC000, 16K)
SRAM_END(0xFF8F0000)
}