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authorSugnan Prabhu S <sugnan.prabhu.s@intel.com>2021-03-26 10:58:49 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-03-30 15:37:18 +0000
commitf040f759d9e1a8107473140eb0f4dc1c99d39a1a (patch)
tree292b9a42cdb0c4b5395a92d2eef5d20d45a09120 /src
parent3d5319eb5ad135c016430a971dfab0eec66bbfde (diff)
downloadcoreboot-f040f759d9e1a8107473140eb0f4dc1c99d39a1a.tar.xz
soc/intel/alderlake: Enable logging of wake sources for S0ix
This change adds elog.c and xhci.c to smm-y for alderlake platforms to enable the logging of wake sources in eventlog for S0ix. BUG=b:183684923 TEST=Verified on Brya that entry/exit for S0ix are logged in eventlogs. 295 | 2021-03-29 10:31:48 | S0ix Enter 296 | 2021-03-29 10:31:58 | S0ix Exit 297 | 2021-03-29 10:31:58 | Wake Source | RTC Alarm | 0 298 | 2021-03-29 10:32:30 | S0ix Enter 299 | 2021-03-29 10:32:55 | S0ix Exit 300 | 2021-03-29 10:32:55 | Wake Source | Power Button | 0 301 | 2021-03-29 10:32:55 | EC Event | Power Button 305 | 2021-03-29 10:43:13 | S0ix Enter 306 | 2021-03-29 10:43:14 | S0ix Exit 307 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0 308 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI | 0 309 | 2021-03-29 10:43:14 | Wake Source | PME - XHCI (USB 2.0 port) | 8 310 | 2021-03-29 10:43:14 | Wake Source | GPE # | 109 Change-Id: Icc836caa797d3bc4e782c6a51492de23e7b49b71 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51839 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/alderlake/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc
index 20e2fb3976..5c1617ba91 100644
--- a/src/soc/intel/alderlake/Makefile.inc
+++ b/src/soc/intel/alderlake/Makefile.inc
@@ -45,11 +45,13 @@ ramstage-y += soundwire.c
ramstage-y += systemagent.c
ramstage-y += xhci.c
+smm-y += elog.c
smm-y += gpio.c
smm-y += p2sb.c
smm-y += pmutil.c
smm-y += smihandler.c
smm-y += uart.c
+smm-y += xhci.c
CPPFLAGS_common += -I$(src)/soc/intel/alderlake
CPPFLAGS_common += -I$(src)/soc/intel/alderlake/include