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authorStefan Reinauer <stepan@coresystems.de>2010-02-04 11:05:59 +0000
committerStefan Reinauer <stepan@openbios.org>2010-02-04 11:05:59 +0000
commitf14e69bc622e43d11aab8dd78d68e05aef0df3c3 (patch)
treef084f92c1f3e29fc43a0de6789b015b0a1a96ce4 /src
parentd8ab6bd0db3e87948b874ae69bf2163bd1982680 (diff)
downloadcoreboot-f14e69bc622e43d11aab8dd78d68e05aef0df3c3.tar.xz
typo
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5085 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/slot_2/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/intel/slot_2/Kconfig b/src/cpu/intel/slot_2/Kconfig
index e87adb6247..82462c3849 100644
--- a/src/cpu/intel/slot_2/Kconfig
+++ b/src/cpu/intel/slot_2/Kconfig
@@ -29,5 +29,5 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex
default 0x01000
- depends on CPU_INTEL_SLOT2
+ depends on CPU_INTEL_SLOT_2