diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-03-22 22:25:37 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-29 20:00:39 +0100 |
| commit | f567f16af4c3cbfcadc3bc5c44b569a592829262 (patch) | |
| tree | e3a51905dc3ee22e6ffcd8047aed682d463ccfc9 /src | |
| parent | fcfe67c3b2b3391a8131eb26cc546a9afaa28822 (diff) | |
| download | coreboot-f567f16af4c3cbfcadc3bc5c44b569a592829262.tar.xz | |
sandybridge: add option to mark graphics memory write-combining.
The graphics memory can be accessed in a faster manner by
setting it to write-combing mode. Add an option to enable
write-combining for the graphics memory.
Change-Id: I7d37fd78906262aabef92c2b4f4cab0e3f7e4f6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 8 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/gma.c | 19 |
2 files changed, 26 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 56d2cd7a38..6c9ae99fcd 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -107,6 +107,14 @@ config DCACHE_RAM_MRC_VAR_SIZE hex default 0x4000 +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index b9a07a2d72..853139eddf 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -664,12 +664,29 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void gma_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + +#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB + struct resource *res; + + /* Set the graphics memory to write combining. */ + res = find_resource(dev, PCI_BASE_ADDRESS_2); + if (res == NULL) { + printk(BIOS_DEBUG, "gma: memory resource not found.\n"); + return; + } + res->flags |= IORESOURCE_WRCOMB; +#endif +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init, |