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authorMeera Ravindranath <meera.ravindranath@intel.com>2020-11-12 16:29:24 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-11-27 05:10:12 +0000
commitf71572605a2b5438da3f0bacd99bd97a491d4620 (patch)
tree25c35d7b274d106dda431751282e2d885057527c /src
parent99eed832aedf8557082bb647b5c8e6cdb016f23a (diff)
downloadcoreboot-f71572605a2b5438da3f0bacd99bd97a491d4620.tar.xz
soc/intel/jasperlake: Enable VT-d and generate DMAR Table
Update UPDs required for the creation of DMAR table. By default coreboot was not generating DMAR table for IOMMU which was resulting in below error message in kernel: DMAR: [Firmware Bug]: No DRHD structure found in DMAR table DMAR: No DMAR devices found These changes will publish DMAR table through ACPI and will not result in the above error. BUG=b:170261791 BRANCH=dedede TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists. Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/jasperlake/romstage/fsp_params.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c
index 528ef0fd21..cd70807516 100644
--- a/src/soc/intel/jasperlake/romstage/fsp_params.c
+++ b/src/soc/intel/jasperlake/romstage/fsp_params.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/device.h>
#include <fsp/util.h>
+#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/soc_chip.h>
@@ -81,6 +82,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
/* VT-d config */
m_cfg->VtdDisable = 0;
+ m_cfg->VtdIopEnable = 0x1;
+
+ if (m_cfg->InternalGfx) {
+ m_cfg->VtdIgdEnable = 0x1;
+ m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
+ }
+
+ if (m_cfg->SaIpuEnable) {
+ m_cfg->VtdIpuEnable = 0x1;
+ m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS;
+ }
+ m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS;
m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE;
m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE];