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authorHung-Te Lin <hungte@chromium.org>2018-09-13 00:18:27 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-16 08:35:12 +0000
commitf89c56a54d62495804167eef40b2718cfdade185 (patch)
treeb439a41759e00e674e10acba8a03d0d67ccff77a /src
parentf349672966fcde4f943c2a5de3c086971aaded44 (diff)
downloadcoreboot-f89c56a54d62495804167eef40b2718cfdade185.tar.xz
google/kukui: Notify EC that AP is in S0
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side, pad R23) that is supposed to be high in S0, and low in S3 (and X/don't care in S5). This should be set as early as possible in bootblock. BUG=b:113367227 TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high. BRANCH=None Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/kukui/bootblock.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c
index a9bad4e0bc..07285882d7 100644
--- a/src/mainboard/google/kukui/bootblock.c
+++ b/src/mainboard/google/kukui/bootblock.c
@@ -21,6 +21,7 @@
#include "gpio.h"
#define BOOTBLOCK_EN_L (GPIO(KPROW0))
+#define AP_IN_SLEEP_L (GPIO(SRCLKENA0))
void bootblock_mainboard_init(void)
{
@@ -29,6 +30,9 @@ void bootblock_mainboard_init(void)
/* Turn on real eMMC. */
gpio_output(BOOTBLOCK_EN_L, 1);
+ /* Declare we are in S0 */
+ gpio_output(AP_IN_SLEEP_L, 1);
+
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz);
mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz);
}