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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-21 21:27:11 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-22 18:39:27 +0000
commitfca9907c498047fba6d8cb318aebea95d7804ea5 (patch)
tree3a7db3459dfbf7351ccf044f6e3a854383f798d8 /src
parentca7580c064735dd15679da989eb7304642c2c0ed (diff)
downloadcoreboot-fca9907c498047fba6d8cb318aebea95d7804ea5.tar.xz
sb/intel/i82870: Drop unused file
Change-Id: I024805769ad05f995a23669a82f5482ce3e7ae70 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/intel/i82870/Makefile.inc1
-rw-r--r--src/southbridge/intel/i82870/pci_parity.c35
2 files changed, 0 insertions, 36 deletions
diff --git a/src/southbridge/intel/i82870/Makefile.inc b/src/southbridge/intel/i82870/Makefile.inc
index 790bd01513..d6ae171926 100644
--- a/src/southbridge/intel/i82870/Makefile.inc
+++ b/src/southbridge/intel/i82870/Makefile.inc
@@ -2,6 +2,5 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82870),y)
ramstage-y += ioapic.c
ramstage-y += pcibridge.c
-#ramstage-y += pci_parity.c
endif
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
deleted file mode 100644
index 3bb05ccf03..0000000000
--- a/src/southbridge/intel/i82870/pci_parity.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <pci.h>
-#include <printk.h>
-#
-
-void p64h2_pci_parity_enable(void)
-{
- uint8_t reg;
-
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
-
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
-
- return;
-}