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authorFurquan Shaikh <furquan@google.com>2020-07-21 22:29:49 -0700
committerFelix Held <felix-coreboot@felixheld.de>2020-07-23 14:11:16 +0000
commitfd4fbe8148dc4f18e13c2008466de50bb2966a64 (patch)
treea62e3b1da960b64a2434b64a1d4e3c52777f7f31 /src
parent65e111774113a03bb4c6752c963f15f0d524aaae (diff)
downloadcoreboot-fd4fbe8148dc4f18e13c2008466de50bb2966a64.tar.xz
mb/google/zork: Configure all pads in ramstage for dalboz reference
This change configures all missing pads in ramstage for dalboz reference. This ensures that the state of all pads is set correctly for the payload/OS. Also, all the pads for the platform are configured in baseboard gpio table in ramstage to ensure that variants can override any pads if required. BUG=b:154351731 Change-Id: Ia30da908d3827177a7b3594ffba38bff81018ab9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c46
1 files changed, 44 insertions, 2 deletions
diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
index 3ab3e10add..26fd686554 100644
--- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
@@ -16,6 +16,8 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_1, SYS_RESET_L, PULL_NONE),
/* PCIE_WAKE_L */
PAD_NF(GPIO_2, WAKE_L, PULL_NONE),
+ /* H1_FCH_INT_ODL */
+ PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
/* PEN_DETECT_ODL */
PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S3),
/* PEN_POWER_EN - Enabled*/
@@ -34,12 +36,17 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_GPI(GPIO_11, PULL_NONE),
/* USI_INT_ODL */
PAD_GPI(GPIO_12, PULL_NONE),
+ /* GPIO_13 - GPIO_15: Not available */
/* USB_OC0_L - USB C0/A0 */
PAD_NF(GPIO_16, USB_OC0_L, PULL_NONE),
/* USB_OC1_L - USB C1 */
PAD_NF(GPIO_17, USB_OC1_L, PULL_NONE),
/* WIFI_DISABLE */
PAD_GPO(GPIO_18, LOW),
+ /* I2C3_SCL - H1 */
+ PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
+ /* I2C3_SDA - H1 */
+ PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
/* EMMC_CMD */
PAD_NF(GPIO_21, EMMC_CMD, PULL_NONE),
/* EC_FCH_SCI_ODL */
@@ -48,10 +55,24 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_23, AC_PRES, PULL_UP),
/* EC_FCH_WAKE_L */
PAD_SCI(GPIO_24, PULL_NONE, EDGE_LOW),
+ /* GPIO_25: Not available */
+ /* PCIE_RST0_L - Fixed timings */
+ PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
+ /* GPIO_27: Configured in bootblock. */
+ /* GPIO_28: Not available */
+ /* GPIO_29: Handled in bootblock for wifi power/reset control. */
+ /* FCH_ESPI_EC_CS_L */
+ PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* EC_AP_INT_ODL (Sensor Framesync) */
PAD_GPI(GPIO_31, PULL_NONE),
/* TP */
PAD_NC(GPIO_32),
+ /* GPIO_33 - GPIO_39: Not available */
+ /* NVME_AUX_RESET_L */
+ PAD_GPO(GPIO_40, HIGH),
+ /* GPIO_41: Not available */
+ /* GPIO_42: Handled in bootblock for wifi power/reset control. */
+ /* GPIO_43 - GPIO_66: Not available */
/* DMIC_SEL */
/*
* Make sure Ext ROM Sharing is disabled before using this GPIO. Otherwise SPI flash
@@ -60,18 +81,20 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_GPO(GPIO_67, LOW), // Select Camera 1 Dmic
/* EMMC_RESET */
PAD_GPO(GPIO_68, LOW),
- /* RAM ID 3*/
+ /* RAM ID 3 */
PAD_GPI(GPIO_69, PULL_NONE),
/* EMMC_CLK */
PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE),
+ /* GPIO_71 - GPIO_73: Not available */
/* EMMC_DATA4 */
PAD_NF(GPIO_74, EMMC_DATA4, PULL_NONE),
/* EMMC_DATA6 */
PAD_NF(GPIO_75, EMMC_DATA6, PULL_NONE),
/* EN_PWR_CAMERA */
PAD_GPO(GPIO_76, HIGH),
+ /* GPIO_77 - GPIO_83: Not available */
/* UNUSED */
- PAD_GPO(GPIO_84, HIGH),
+ PAD_NC(GPIO_84),
/* APU_EDP_BL_DISABLE TODP: Set low in depthcharge */
PAD_GPO(GPIO_85, HIGH),
/* RAM ID 2 */
@@ -86,6 +109,9 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_GPI(GPIO_90, PULL_NONE),
/* EN_SPKR TODO: Verify driver enables this (add to ACPI) */
PAD_GPO(GPIO_91, LOW),
+ /* CLK_REQ0_L - WIFI */
+ PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
+ /* GPIO_93 - GPIO_103: Not available */
/* EMMC_DATA0 */
PAD_NF(GPIO_104, EMMC_DATA0, PULL_NONE),
/* EMMC_DATA1 */
@@ -94,26 +120,42 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
PAD_NF(GPIO_106, EMMC_DATA2, PULL_NONE),
/* EMMC_DATA3 */
PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE),
+ /* ESPI_ALERT_L */
+ PAD_NF(GPIO_108, ESPI_ALERT_L, PULL_UP),
/* EMMC_DS */
PAD_NF(GPIO_109, EMMC_DS, PULL_NONE),
+ /* GPIO_110 - GPIO112: Not available */
/* I2C2_SCL - USI/Touchpad */
PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
/* I2C2_SDA - USI/Touchpad */
PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
+ /* CLK_REQ1_L - SD Card */
+ PAD_NF(GPIO_115, CLK_REQ1_L, PULL_NONE),
+ /* CLK_REQ2_L - NVMe */
+ PAD_NF(GPIO_116, CLK_REQ2_L, PULL_NONE),
+ /* GPIO_117 - GPIO_128: Not available */
/* KBRST_L */
PAD_NF(GPIO_129, KBRST_L, PULL_NONE),
+ /* GPIO_130 - GPIO_131: Not available */
/* RAM ID 0 */
PAD_GPI(GPIO_132, PULL_NONE),
+ /* GPIO_133 - GPIO_134: Not available */
/* DEV_BEEP_CODEC_IN (Dev beep Data out) */
PAD_GPI(GPIO_135, PULL_NONE),
+ /* UART0_RXD - DEBUG */
+ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
/* BIOS_FLASH_WP_ODL */
PAD_GPI(GPIO_137, PULL_NONE),
+ /* UART0_TXD - DEBUG */
+ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
/* DEV_BEEP_BCLK */
PAD_GPI(GPIO_139, PULL_NONE),
/* USI_RESET */
PAD_GPO(GPIO_140, HIGH),
/* USB_HUB_RST_L */
PAD_GPO(GPIO_141, HIGH),
+ /* SD_AUX_RESET_L */
+ PAD_GPO(GPIO_142, HIGH),
/* BT_DISABLE */
PAD_GPO(GPIO_143, LOW),
/*