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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-15 21:37:38 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-20 15:47:39 +0000 |
| commit | fedaac84da5bcfd035e0e348150db8cf3d800726 (patch) | |
| tree | a60bb306e8539a6bdad743e5a381129e011c20b0 /src | |
| parent | fa0df7d316fc9b4be825b7ad60ada844660202c6 (diff) | |
| download | coreboot-fedaac84da5bcfd035e0e348150db8cf3d800726.tar.xz | |
AGESA,binaryPI: Enable lapic early for udelay()
Change-Id: I7200ac0256748d9372fc39be27b86d1c93b38321
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/amd/pi/00630F01/fixme.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/pi/00660F01/fixme.c | 6 | ||||
| -rw-r--r-- | src/cpu/amd/pi/00730F01/fixme.c | 6 | ||||
| -rw-r--r-- | src/drivers/amd/agesa/bootblock.c | 7 |
4 files changed, 7 insertions, 18 deletions
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 12f8062dfa..d94215a44b 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -85,10 +85,4 @@ void amd_initmmio(void) LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)){ - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 237d52b2c1..7d71e2ea1a 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -91,10 +91,4 @@ void amd_initmmio(void) LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index a0621cbb7f..7edd1b8fa2 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -96,10 +96,4 @@ void amd_initmmio(void) LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); - - if (CONFIG(UDELAY_LAPIC)) { - LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); - MsrReg |= 1 << 11; - LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); - } } diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 3763b98a3a..91fcc6b994 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -18,6 +18,7 @@ #include <amdblocks/biosram.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/lapic.h> #define EARLY_VMTRR_FLASH 6 @@ -33,6 +34,9 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) enable_pci_mmconf(); set_early_mtrrs(); + if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + bootblock_main_with_basetime(base_timestamp); } @@ -41,6 +45,9 @@ asmlinkage void ap_bootblock_c_entry(void) enable_pci_mmconf(); set_early_mtrrs(); + if (CONFIG(UDELAY_LAPIC)) + enable_lapic(); + void (*ap_romstage_entry)(void) = get_ap_entry_ptr(); ap_romstage_entry(); /* execution does not return */ halt(); |