diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-06-17 16:03:18 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-25 11:57:32 +0000 |
| commit | 01e38559c36e5ca9e1cf69c7a674bf10aa156dd9 (patch) | |
| tree | 8805140d953fd65ccee600bbc4b418594d2e672b /src | |
| parent | 951a409f669138bae25e255ec131b5fe0b0daec0 (diff) | |
| download | coreboot-01e38559c36e5ca9e1cf69c7a674bf10aa156dd9.tar.xz | |
drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1
Not all FSPs based on FSP 2.1 supports the feature of external PPI
interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE.
Deselect FSP_PEIM_TO_PEIM_INTERFACE when PLATFORM_USES_FSP2_1 is
selected.
Update Kconfig of SOCs affected (icelake, jasperlake, tigerlake).
Change-Id: I5df03f8bcf15c9e05c9fd904a79f740260a3aed7
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/drivers/intel/fsp2_0/Kconfig | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 1 |
5 files changed, 5 insertions, 4 deletions
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index fc1eaf66b4..3caa04ac25 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -11,12 +11,10 @@ config PLATFORM_USES_FSP2_1 default n select PLATFORM_USES_FSP2_0 select FSP_USES_CB_STACK - select FSP_PEIM_TO_PEIM_INTERFACE help Include FSP 2.1 wrappers and functionality. - Features added into FSP 2.1 specification that impacts coreboot are: + Feature added into FSP 2.1 specification that impacts coreboot is: 1. Remove FSP stack switch and use the same stack with boot firmware - 2. FSP should support external PPI interface pulled in via FSP_PEIM_TO_PEIM_INTERFACE config PLATFORM_USES_FSP2_2 bool diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d3b2..3c29b2401e 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -61,7 +61,7 @@ config USE_INTEL_FSP_MP_INIT config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI bool "Perform MP Initialization by FSP using coreboot MP PPI service" depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 + default y if FSP_PEIM_TO_PEIM_INTERFACE default n help This option allows FSP to make use of MP services PPI published by diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 83a62ca770..f58aa3354e 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -31,6 +31,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 72b0c5ef9d..89bbdd3614 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index f502940b0b..c30519c2fa 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS select PARALLEL_MP_AP_WORK select MICROCODE_BLOB_UNDISCLOSED select PLATFORM_USES_FSP2_1 + select FSP_PEIM_TO_PEIM_INTERFACE select REG_SCRIPT select SMP select PMC_GLOBAL_RESET_ENABLE_LOCK |