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authorMichael Niewöhner <foss@mniewoehner.de>2020-10-20 14:27:09 +0200
committerNico Huber <nico.h@gmx.de>2020-10-24 09:53:26 +0000
commit062b92ef654a97648380a1a9a9fe34229ee76e31 (patch)
tree0c64f02b62684a040ac0844c8af9c160fcaff1b2 /src
parent10ae1cf2cda38e681849dcc9e6e86ee3330a8b17 (diff)
downloadcoreboot-062b92ef654a97648380a1a9a9fe34229ee76e31.tar.xz
cpu/intel/common: rework code previously moved to common cpu code
Rework the code moved to common code in CB:46274. This involves simplification by using appropriate helpers for MSR and CPUID, using macros instead of plain values for MSRs and cpu features and adding documentation to the header. Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/common/common.h6
-rw-r--r--src/cpu/intel/common/common_init.c36
-rw-r--r--src/include/cpu/intel/msr.h1
-rw-r--r--src/include/cpu/x86/msr.h3
4 files changed, 18 insertions, 28 deletions
diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h
index dd8c2b8a27..fdacd1f74b 100644
--- a/src/cpu/intel/common/common.h
+++ b/src/cpu/intel/common/common.h
@@ -33,10 +33,16 @@ bool intel_ht_sibling(void);
*/
void set_aesni_lock(void);
+/* Enable local CPU APIC TPR (Task Priority Register) updates */
void enable_lapic_tpr(void);
+/* Enable DCA (Direct Cache Access) */
void configure_dca_cap(void);
+/*
+ * Set EPB (Energy Performance Bias)
+ * Possible values are 0 (performance) to 15 (powersave).
+ */
void set_energy_perf_bias(u8 policy);
#endif
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index f4bf245c2f..d0b66d4815 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -8,6 +8,8 @@
#include <cpu/x86/msr.h>
#include "common.h"
+#define CPUID_6_ECX_EPB (1 << 3)
+
void set_vmx_and_lock(void)
{
set_feature_ctrl_vmx();
@@ -290,42 +292,22 @@ void set_aesni_lock(void)
void enable_lapic_tpr(void)
{
- msr_t msr;
-
- msr = rdmsr(MSR_PIC_MSG_CONTROL);
- msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
- wrmsr(MSR_PIC_MSG_CONTROL, msr);
+ msr_unset(MSR_PIC_MSG_CONTROL, TPR_UPDATES_DISABLE);
}
void configure_dca_cap(void)
{
- uint32_t feature_flag;
- msr_t msr;
-
- /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
- feature_flag = cpu_get_feature_flags_ecx();
- if (feature_flag & CPUID_DCA) {
- msr = rdmsr(IA32_PLATFORM_DCA_CAP);
- msr.lo |= 1;
- wrmsr(IA32_PLATFORM_DCA_CAP, msr);
- }
+ if (cpu_get_feature_flags_ecx() & CPUID_DCA)
+ msr_set(IA32_PLATFORM_DCA_CAP, DCA_TYPE0_EN);
}
void set_energy_perf_bias(u8 policy)
{
- msr_t msr;
- int ecx;
+ u8 epb = policy & ENERGY_POLICY_MASK;
- /* Determine if energy efficient policy is supported. */
- ecx = cpuid_ecx(0x6);
- if (!(ecx & (1 << 3)))
+ if (!(cpuid_ecx(6) & CPUID_6_ECX_EPB))
return;
- /* Energy Policy is bits 3:0 */
- msr = rdmsr(IA32_ENERGY_PERF_BIAS);
- msr.lo &= ~0xf;
- msr.lo |= policy & 0xf;
- wrmsr(IA32_ENERGY_PERF_BIAS, msr);
-
- printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", policy);
+ msr_unset_and_set(IA32_ENERGY_PERF_BIAS, ENERGY_POLICY_MASK, epb);
+ printk(BIOS_DEBUG, "cpu: energy policy set to %u\n", epb);
}
diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h
index 9dbea776dd..a2165f365a 100644
--- a/src/include/cpu/intel/msr.h
+++ b/src/include/cpu/intel/msr.h
@@ -10,5 +10,6 @@
#define AESNI_LOCK (1 << 0)
#define MSR_PIC_MSG_CONTROL 0x2e
+#define TPR_UPDATES_DISABLE (1 << 10)
#endif /* CPU_INTEL_MSR_H */
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 058419fd1e..5ae3ddf93a 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -48,11 +48,12 @@
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
+#define ENERGY_POLICY_MASK 0xf
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
-#define IA32_PLATFORM_DCA_CAP 0x1f8
#define SMRR_PHYSBASE_MSR 0x1F2
#define SMRR_PHYSMASK_MSR 0x1F3
#define IA32_PLATFORM_DCA_CAP 0x1f8
+#define DCA_TYPE0_EN (1 << 0)
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401