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authorAngel Pons <th3fanbus@gmail.com>2021-03-26 19:07:49 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-04-02 14:34:23 +0000
commit07ccc8d9cd52f484f75761d52b4efbb99029d473 (patch)
tree068d28f92a9b141072e81e25dc8fbf6bd9d83a79 /src
parentb77f01642cd7332e258e1c2ef51c470b96466b4f (diff)
downloadcoreboot-07ccc8d9cd52f484f75761d52b4efbb99029d473.tar.xz
nb/intel/pineview: Correct COMP register write
Reference code does an and-or operation with zero as or-value, reading and writing to the same address. The accessed register is 32-bit, and reference code programs bits 22, 21, 20, 16 to zero. However, coreboot code reads the value from bits 7..0 instead. Correct this. Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/pineview/raminit.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 7b9f410327..391aa82902 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -1401,8 +1401,8 @@ static void sdram_rcomp(struct sysinfo *s)
MCHBAR8_AND(XCOMPSDR0BNS, ~(1 << 5));
FOR_EACH_RCOMP_GROUP(i) {
- /* FIXME: This should be an _AND_OR */
- MCHBAR8(C0RCOMPCTRLx(i) + 2) = MCHBAR8(C0RCOMPCTRLx(i)) & ~0x71;
+ /* POR values are zero */
+ MCHBAR8_AND(C0RCOMPCTRLx(i) + 2, ~0x71);
}
if ((MCHBAR32(COMPCTRL1) & (1 << 30)) == 0) {