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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-01 07:13:09 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-05 14:38:17 +0000
commit092fe558ee20950faf29d8e7d581a2631e6e1bb4 (patch)
treed362ab8d09e69f0c3b1e0ffc8954eafd5eda9fce /src
parentfe3250dbe6b27df7aa0cf0fa432a0b6a1ca5ebb8 (diff)
downloadcoreboot-092fe558ee20950faf29d8e7d581a2631e6e1bb4.tar.xz
intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER
Note that due to UNKNOWN_TSC_RATE, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the cpu. Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/cpu/intel/slot_1/Kconfig3
-rw-r--r--src/northbridge/intel/i440bx/Kconfig1
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 3d0522a09d..10001bdc5f 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -24,7 +24,8 @@ config SLOT_SPECIFIC_OPTIONS # dummy
select CPU_INTEL_MODEL_6BX
select CPU_INTEL_MODEL_6XX
select NO_SMM
- select NO_MONOTONIC_TIMER
+ select UDELAY_TSC
+ select TSC_MONOTONIC_TIMER
select UNKNOWN_TSC_RATE
config DCACHE_RAM_BASE
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index 45cdd9c7f1..df1e3650a4 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -17,7 +17,6 @@ config NORTHBRIDGE_INTEL_I440BX
bool
select NO_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
- select UDELAY_IO
config SDRAMPWR_4DIMM
bool