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authorCaveh Jalali <caveh@google.com>2018-01-23 22:15:24 -0800
committerAaron Durbin <adurbin@chromium.org>2018-01-25 15:56:29 +0000
commit1428f0176d7eb5d4eb62bffefefbab54e690d0a8 (patch)
treefb287584d963da47166ecf600eba44eaec2077f0 /src
parent6de0cd2b7d7c6611ac743575032d4163a6759f8c (diff)
downloadcoreboot-1428f0176d7eb5d4eb62bffefefbab54e690d0a8.tar.xz
soc/intel/cannonlake: enable pch link in bootblock
This moves the call to pch_enable_lpc() from romstage to bootblock. In other words, it happens earlier in the boot process. Turns out, we need this to talk to the EC to determine if we're in recovery mode or not. BUG=b:69011806 TEST=boots to linux Change-Id: I899bf343d705fe19a2978917bc88990495ebb5a3 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/cannonlake/Makefile.inc1
-rw-r--r--src/soc/intel/cannonlake/bootblock/pch.c4
-rw-r--r--src/soc/intel/cannonlake/romstage/romstage.c3
3 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index bfc52ce418..47f06aa47d 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -18,6 +18,7 @@ bootblock-y += gspi.c
bootblock-y += i2c.c
bootblock-y += memmap.c
bootblock-y += spi.c
+bootblock-y += lpc.c
bootblock-$(CONFIG_UART_DEBUG) += uart.c
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index ae413d5813..8e4f7fd81e 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -17,6 +17,7 @@
#include <device/device.h>
#include <intelblocks/fast_spi.h>
#include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/rtc.h>
#include <intelblocks/pmclib.h>
@@ -174,6 +175,9 @@ void pch_early_iorange_init(void)
dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN;
pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
+
+ /* Program generic IO Decode Range */
+ pch_enable_lpc();
}
void pch_early_init(void)
diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c
index 2673f3700b..8b3794f4e9 100644
--- a/src/soc/intel/cannonlake/romstage/romstage.c
+++ b/src/soc/intel/cannonlake/romstage/romstage.c
@@ -22,7 +22,6 @@
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/cse.h>
-#include <intelblocks/lpc_lib.h>
#include <intelblocks/pmclib.h>
#include <memory_info.h>
#include <soc/iomap.h>
@@ -47,8 +46,6 @@ asmlinkage void car_stage_entry(void)
/* initialize Heci interface */
heci_init(HECI1_BASE_ADDRESS);
- /* Program LPC generic decoding */
- pch_enable_lpc();
timestamp_add_now(TS_START_ROMSTAGE);
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);