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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-08-05 07:58:05 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-10 10:44:59 +0000 |
| commit | 199a69292d8d3a3bc526b70b01f2eea64773346f (patch) | |
| tree | 4fbfd5f4adca19b6232946bd6a2ce7d23e0c6d4c /src | |
| parent | c56b90703f68c6c77fa876b910c0082b611b7471 (diff) | |
| download | coreboot-199a69292d8d3a3bc526b70b01f2eea64773346f.tar.xz | |
soc/intel/cannonlake/acpi/serialio.asl: Don't advertise unavailable devices
On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.1 and
0:19.2 can't be detected using standard PCI probing.
Remove I2C4, I2C5 and UART2 from generic ASL code on PCH-H platforms
that advertise its PCI conformance by the _ADR attribute.
Change-Id: I89f9ab7d4afb2e7d1b1e24d072adf99e0da6fecf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/serialio.asl | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/acpi/serialio.asl b/src/soc/intel/cannonlake/acpi/serialio.asl index e4a675e335..0551191271 100644 --- a/src/soc/intel/cannonlake/acpi/serialio.asl +++ b/src/soc/intel/cannonlake/acpi/serialio.asl @@ -26,6 +26,7 @@ Device (I2C3) Name (_DDN, "Serial IO I2C Controller 3") } +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) Device (I2C4) { Name (_ADR, 0x00190000) @@ -37,6 +38,7 @@ Device (I2C5) Name (_ADR, 0x00190001) Name (_DDN, "Serial IO I2C Controller 5") } +#endif Device (SPI0) { @@ -68,8 +70,10 @@ Device (UAR1) Name (_DDN, "Serial IO UART Controller 1") } +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) Device (UAR2) { Name (_ADR, 0x00190002) Name (_DDN, "Serial IO UART Controller 2") } +#endif |