diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2021-01-19 08:26:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-22 14:27:45 +0000 |
| commit | 1b5b41a790110a44dd7964fbd426becda4183a62 (patch) | |
| tree | 59c38c15d3d6b54fac29c14bbbec4c23dee12bd5 /src | |
| parent | 8ab253c9a91da036a7d079028623b723a78c1eae (diff) | |
| download | coreboot-1b5b41a790110a44dd7964fbd426becda4183a62.tar.xz | |
mb/prodrive/hermes: Fix 30 second boot delay
The PMC doesn't response any more due to invalid CNVi GPIO
configuration. This caused a 30 second boot delay in FSP-S.
Use the same values as FSP-S does. Always disable external I2S BT
audio and use NF3 for pad GPP_D5 and GPP_D6.
Tested on Prodrive hermes:
No boot delay can be observed any more.
Change-Id: I6f4a954786ec21512b0dce908d333952e96de048
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49678
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/prodrive/hermes/variants/baseboard/gpio.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c index c95e9d2301..7f81842e21 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c @@ -102,11 +102,11 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_D4, NONE), - /* I2S2 */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* M2_E_BT_PCMFRM_CRF_RST_n */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* M2_E_BT_PCMOUT_CLKREQ0 */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* M2_E_BT_PCMIN */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* M2_E_BT_PCMCLK */ + /* CNVi */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF3), /* M2_E_BT_PCMFRM_CRF_RST_n */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), /* M2_E_BT_PCMOUT_CLKREQ0 */ + PAD_NC(GPP_D7, NONE), /* M2_E_BT_PCMIN */ + PAD_NC(GPP_D8, NONE), /* M2_E_BT_PCMCLK */ /* ISH SPI */ PAD_NC(GPP_D9, NONE), |