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authorSubrata Banik <subrata.banik@intel.com>2018-11-26 15:43:18 +0530
committerPatrick Georgi <pgeorgi@google.com>2018-11-28 11:50:19 +0000
commit1c329a05de8b821cd85c25cf8ab7d1e73714073f (patch)
tree01974040755006efe32807329471e17a703f9bf6 /src
parent190e5bee4a75208d1975c639321f46d4425e3583 (diff)
downloadcoreboot-1c329a05de8b821cd85c25cf8ab7d1e73714073f.tar.xz
soc/intel/icelake: Fix IO decode setup
Make pch_early_iorange_init() function similar to soc/intel/cannonlake/bootblock/pch.c while fixing below issue: * COM1 not being enabled properly. TEST=Able to get serial output from an 8250IO UART device at the standard 0x3f8 base address. Change-Id: I5ab02f46d27e667be3d9328d94b634ef04038d2f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/29835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/icelake/bootblock/pch.c41
-rw-r--r--src/soc/intel/icelake/include/soc/lpc.h10
2 files changed, 29 insertions, 22 deletions
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c
index 96722e21be..5268856007 100644
--- a/src/soc/intel/icelake/bootblock/pch.c
+++ b/src/soc/intel/icelake/bootblock/pch.c
@@ -43,6 +43,9 @@
#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
+#define PCR_DMI_DMICTL 0x2234
+#define PCR_DMI_DMICTL_SRLOCK (1 << 31)
+
#define PCR_DMI_ACPIBA 0x27B4
#define PCR_DMI_ACPIBDID 0x27B8
#define PCR_DMI_PMBASEA 0x27AC
@@ -146,24 +149,38 @@ static void soc_config_tco(void)
outw(tcocnt, tcobase + TCO1_CNT);
}
+static int pch_check_decode_enable(void)
+{
+ uint32_t dmi_control;
+
+ /*
+ * This cycle decoding is only allowed to set when
+ * DMICTL.SRLOCK is 0.
+ */
+ dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL);
+ if (dmi_control & PCR_DMI_DMICTL_SRLOCK)
+ return -1;
+ return 0;
+}
+
void pch_early_iorange_init(void)
{
- uint16_t dec_rng, dec_en = 0;
+ uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+ LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
/* IO Decode Range */
- if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO) &&
- IS_ENABLED(CONFIG_UART_DEBUG)) {
- dec_rng = COMA_RANGE | (COMB_RANGE << 4);
- dec_en = COMA_LPC_EN | COMB_LPC_EN;
- pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, dec_rng);
- pcr_write16(PID_DMI, PCR_DMI_LPCIOD, dec_rng);
- }
+ if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
+ lpc_io_setup_comm_a_b();
/* IO Decode Enable */
- dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN |
- LPC_IOE_KBC_60_64;
- pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en);
- pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en);
+ if (pch_check_decode_enable() == 0) {
+ io_enables = lpc_enable_fixed_io_ranges(io_enables);
+ /*
+ * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
+ * value program in LPC PCI offset 82h.
+ */
+ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
+ }
/* Program generic IO Decode Range */
pch_enable_lpc();
diff --git a/src/soc/intel/icelake/include/soc/lpc.h b/src/soc/intel/icelake/include/soc/lpc.h
index dfcfa353c8..ebfcaa867f 100644
--- a/src/soc/intel/icelake/include/soc/lpc.h
+++ b/src/soc/intel/icelake/include/soc/lpc.h
@@ -32,16 +32,6 @@
#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
#define LPC_EN 0x82 /* LPC IF Enables Register */
-#define MC2_LPC_EN (1 << 13) /* 0x4e/0x4f */
-#define SE_LPC_EN (1 << 12) /* 0x2e/0x2f */
-#define MC1_LPC_EN (1 << 11) /* 0x62/0x66 */
-#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
-#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
-#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
-#define FDD_LPC_EN (1 << 3) /* Floppy Drive Enable */
-#define LPT_LPC_EN (1 << 2) /* Parallel Port Enable */
-#define COMB_LPC_EN (1 << 1) /* Com Port B Enable */
-#define COMA_LPC_EN (1 << 0) /* Com Port A Enable */
#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */