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| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-03-03 01:43:45 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-10 09:57:41 +0000 |
| commit | 2b4ded0be8c1c01aba566bb4bbccf5169ce133f7 (patch) | |
| tree | 6bfda11d467b172f1de023f19194bace8a773a3f /src | |
| parent | 01ec713c269f68e5a2918cfb8ee14d6d1f40eda8 (diff) | |
| download | coreboot-2b4ded0be8c1c01aba566bb4bbccf5169ce133f7.tar.xz | |
soc/intel/tigerlake: Enable Hybrid storage mode
To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mode for NVMe. The mode can be selected using
the FIT tool at build time.
By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.
BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/fsp_params_tgl.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a6bcf0847f..d2ea0ddd2f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -266,6 +266,11 @@ struct soc_intel_tigerlake_config { uint8_t DdiPort2Ddc; uint8_t DdiPort3Ddc; uint8_t DdiPort4Ddc; + + /* Hybrid storage mode enable (1) / disable (0) + * This mode makes FSP detect Optane and NVME and set PCIe lane mode + * accordingly */ + uint8_t HybridStorageMode; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 0dae0fed47..14997c519a 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -157,6 +157,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; + /* Enable Hybrid storage auto detection */ + params->HybridStorageMode = config->HybridStorageMode; + mainboard_silicon_init_params(params); } |