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authorElyes HAOUAS <ehaouas@noos.fr>2018-06-01 14:45:37 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-04 08:41:55 +0000
commit2bf1d417c542a6e3a5f2fca810c6bc1db2c02377 (patch)
treec460e3545a725c23821710255e2e9d6c7daba461 /src
parentc32c85308f2e8812258c0125b8d2bb01d69dfa3a (diff)
downloadcoreboot-2bf1d417c542a6e3a5f2fca810c6bc1db2c02377.tar.xz
arch/x86: Remove unneeded includes
Change-Id: I0b87e2b36a282c773e5f2f4a96c23aeadecb1300 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/arch/x86/cbmem.c1
-rw-r--r--src/arch/x86/cpu_common.c8
-rw-r--r--src/arch/x86/pci_ops_conf1.c2
3 files changed, 0 insertions, 11 deletions
diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c
index ef53553777..52f8f8a5de 100644
--- a/src/arch/x86/cbmem.c
+++ b/src/arch/x86/cbmem.c
@@ -12,7 +12,6 @@
*/
#include <stdlib.h>
-#include <console/console.h>
#include <cbmem.h>
#include <compiler.h>
#include <arch/acpi.h>
diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c
index 26cf69f6b9..d328fe9030 100644
--- a/src/arch/x86/cpu_common.c
+++ b/src/arch/x86/cpu_common.c
@@ -11,15 +11,7 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
#include <cpu/cpu.h>
-#include <arch/io.h>
-#include <string.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include <device/path.h>
-#include <device/device.h>
-#include <smp/spinlock.h>
#ifndef __x86_64__
/* Standard macro to see if a specific flag is changeable */
diff --git a/src/arch/x86/pci_ops_conf1.c b/src/arch/x86/pci_ops_conf1.c
index a92fd3108f..30cbcb46f1 100644
--- a/src/arch/x86/pci_ops_conf1.c
+++ b/src/arch/x86/pci_ops_conf1.c
@@ -11,10 +11,8 @@
* GNU General Public License for more details.
*/
-#include <console/console.h>
#include <arch/io.h>
#include <device/pci.h>
-#include <device/pci_ids.h>
#include <device/pci_ops.h>
/*
* Functions for accessing PCI configuration space with type 1 accesses