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authorTan, Lean Sheng <lean.sheng.tan@intel.com>2021-01-31 04:39:00 -0800
committerPatrick Georgi <pgeorgi@google.com>2021-04-26 08:32:20 +0000
commit2ffa9c6f2990f695ee567238b372070ab7209df4 (patch)
treefec4dd8008ccf6907159d1c8a583d679cdc2202b /src
parent6e9d8067cab6fdbca64cc168996f2d4b869fd96d (diff)
downloadcoreboot-2ffa9c6f2990f695ee567238b372070ab7209df4.tar.xz
soc/intel/elkhartlake: Remove elog.c
Remove elog.c from EHL soc as EHL does not support chromebook and hence does not need it. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If66adfe15d00feb0a7fb5e1ced92006a4adebdb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50173 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/elkhartlake/Makefile.inc1
-rw-r--r--src/soc/intel/elkhartlake/elog.c117
2 files changed, 0 insertions, 118 deletions
diff --git a/src/soc/intel/elkhartlake/Makefile.inc b/src/soc/intel/elkhartlake/Makefile.inc
index fb6a5c1372..0ac14e6200 100644
--- a/src/soc/intel/elkhartlake/Makefile.inc
+++ b/src/soc/intel/elkhartlake/Makefile.inc
@@ -30,7 +30,6 @@ romstage-y += reset.c
ramstage-y += acpi.c
ramstage-y += chip.c
ramstage-y += cpu.c
-ramstage-y += elog.c
ramstage-y += espi.c
ramstage-y += finalize.c
ramstage-y += fsp_params.c
diff --git a/src/soc/intel/elkhartlake/elog.c b/src/soc/intel/elkhartlake/elog.c
deleted file mode 100644
index 14e463c961..0000000000
--- a/src/soc/intel/elkhartlake/elog.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <bootstate.h>
-#include <console/console.h>
-#include <elog.h>
-#include <intelblocks/pmclib.h>
-#include <soc/pci_devs.h>
-#include <soc/pm.h>
-#include <stdint.h>
-
-static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start)
-{
- int i;
-
- gpe0_sts &= gpe0_en;
-
- for (i = 0; i <= 31; i++) {
- if (gpe0_sts & (1 << i))
- elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start);
- }
-}
-
-static void pch_log_wake_source(const struct chipset_power_state *ps)
-{
- /* Power Button */
- if (ps->pm1_sts & PWRBTN_STS)
- elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0);
-
- /* RTC */
- if (ps->pm1_sts & RTC_STS)
- elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
-
- /* PCI Express (TODO: determine wake device) */
- if (ps->pm1_sts & PCIEXPWAK_STS)
- elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
-
- /* PME (TODO: determine wake device) */
- if (ps->gpe0_sts[GPE_STD] & PME_STS)
- elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
-
- /* Internal PME (TODO: determine wake device) */
- if (ps->gpe0_sts[GPE_STD] & PME_B0_STS)
- elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
-
- /* SMBUS Wake */
- if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS)
- elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
-
- /* Log GPIO events in set 1-3 */
- pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0);
- pch_log_gpio_gpe(ps->gpe0_sts[GPE_63_32], ps->gpe0_en[GPE_63_32], 32);
- pch_log_gpio_gpe(ps->gpe0_sts[GPE_95_64], ps->gpe0_en[GPE_95_64], 64);
- /* Treat the STD as an extension of GPIO to obtain visibility. */
- pch_log_gpio_gpe(ps->gpe0_sts[GPE_STD], ps->gpe0_en[GPE_STD], 96);
-}
-
-static void pch_log_power_and_resets(const struct chipset_power_state *ps)
-{
- /* Thermal Trip */
- if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
- elog_add_event(ELOG_TYPE_THERM_TRIP);
-
- /* PWR_FLR Power Failure */
- if (ps->gen_pmcon_a & PWR_FLR)
- elog_add_event(ELOG_TYPE_POWER_FAIL);
-
- /* SUS Well Power Failure */
- if (ps->gen_pmcon_a & SUS_PWR_FLR)
- elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
-
- /* TCO Timeout */
- if (ps->prev_sleep_state != ACPI_S3 &&
- ps->tco2_sts & TCO_STS_SECOND_TO)
- elog_add_event(ELOG_TYPE_TCO_RESET);
-
- /* Power Button Override */
- if (ps->pm1_sts & PRBTNOR_STS)
- elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
-
- /* RTC reset */
- if (ps->gen_pmcon_b & RTC_BATTERY_DEAD)
- elog_add_event(ELOG_TYPE_RTC_RESET);
-
- /* Host Reset Status */
- if (ps->gen_pmcon_a & HOST_RST_STS)
- elog_add_event(ELOG_TYPE_SYSTEM_RESET);
-
- /* ACPI Wake Event */
- if (ps->prev_sleep_state != ACPI_S0)
- elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
-}
-
-static void pch_log_state(void *unused)
-{
- struct chipset_power_state *ps = pmc_get_power_state();
-
- if (!ps) {
- printk(BIOS_ERR, "chipset_power_state not found!\n");
- return;
- }
-
- /* Power and Reset */
- pch_log_power_and_resets(ps);
-
- /* Wake Sources */
- if (ps->prev_sleep_state > ACPI_S0)
- pch_log_wake_source(ps);
-}
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pch_log_state, NULL);
-
-void elog_gsmi_cb_platform_log_wake_source(void)
-{
- struct chipset_power_state ps;
- pmc_fill_pm_reg_info(&ps);
- pch_log_wake_source(&ps);
-}