diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 18:09:46 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-21 08:03:42 +0000 |
| commit | 3447db5fe451c84c3c8dbb3e4a88c266e6c1d368 (patch) | |
| tree | cb75abb5cf52796a4589e0ffb0cb1a1045d15ef5 /src | |
| parent | f950a7ec6767eee0a857d01e0c3f67ccf36dd8e1 (diff) | |
| download | coreboot-3447db5fe451c84c3c8dbb3e4a88c266e6c1d368.tar.xz | |
nb/intel/sandybridge: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45358
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/registers/host_bridge.h (renamed from src/northbridge/intel/sandybridge/hostbridge_regs.h) | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/registers/mchbar.h (renamed from src/northbridge/intel/sandybridge/mchbar_regs.h) | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 4 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/sandybridge/hostbridge_regs.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h index 2d2fcff3b1..4814b94b6f 100644 --- a/src/northbridge/intel/sandybridge/hostbridge_regs.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ -#define __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ +#define __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ #define EPBAR 0x40 #define MCHBAR 0x48 @@ -60,4 +60,4 @@ #define DIDOR 0xf3 /* Device ID override, for debug and samples only */ -#endif /* __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/registers/mchbar.h index 370dd74381..2fe6b24e76 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ -#define __SANDYBRIDGE_MCHBAR_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__ +#define __SANDYBRIDGE_REGISTERS_MCHBAR_H__ /* * ### IOSAV memory controller interface poking state machine notes ### @@ -533,4 +533,4 @@ #define CRDTCTL4 0x7410 /* Read Return Tracker credits */ #define CRDTLCK 0x77fc -#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 5318d0b245..5c15cb1ad3 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -36,7 +36,7 @@ enum platform_type { /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ @@ -66,7 +66,7 @@ enum platform_type { #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h" /* * EPBAR - Egress Port Root Complex Register Block |