diff options
| author | Cliff Huang <cliff.huang@intel.com> | 2021-02-09 15:16:18 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:26:37 +0000 |
| commit | 3663fb36ec067e2b4cb3fca4429773bc72628ffa (patch) | |
| tree | f306a668f6337b024df3b5220bd30d40af2ef2ab /src | |
| parent | 2eee6c3a7d520101220ed59753df0e62ea549561 (diff) | |
| download | coreboot-3663fb36ec067e2b4cb3fca4429773bc72628ffa.tar.xz | |
mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.
Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 57f36ab9d9..637afab3e2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -19,6 +19,9 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" + # CNVi BT enable/disable + register "CnviBtCore" = "true" + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # M.2 Bluetooth @@ -213,7 +216,6 @@ chip soc/intel/tigerlake device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) - device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 on # SensorHUB 0xA0FC diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 70833eefac..83b924e7b2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -19,6 +19,9 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" register "SmbusEnable" = "1" + # CNVi BT enable/disable + register "CnviBtCore" = "true" + register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # M.2 WWAN register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1 @@ -217,7 +220,6 @@ chip soc/intel/tigerlake device pci 0e.0 off end # VMD 0x9A0B # From PCH EDS(576591) - device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 on # SensorHUB 0xA0FC |