diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-11-27 00:20:18 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-11-29 14:23:03 +0000 |
| commit | 3a873b5c9a70ec41488161b491ffe5ac94bb554e (patch) | |
| tree | 2c37aec29d98972448c5165359e060509b4846e8 /src | |
| parent | f79f00991cd708dd426e5509cbd398e2c1b244ed (diff) | |
| download | coreboot-3a873b5c9a70ec41488161b491ffe5ac94bb554e.tar.xz | |
mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP
TEST=Able to pass MRC training on DDR4/5 SKUs
Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/adlrvp/memory.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index cab4ef93f3..5d374db2a6 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -12,7 +12,7 @@ static const struct mb_cfg ddr4_mem_config = { /* Baseboard Rcomp target values */ .rcomp_targets = {40, 30, 33, 33, 30}, - .dq_pins_interleaved = true, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ @@ -61,7 +61,7 @@ static const struct mb_cfg ddr5_mem_config = { /* Baseboard Rcomp target values */ .rcomp_targets = {50, 30, 30, 30, 27}, - .dq_pins_interleaved = true, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ |