diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2020-01-14 17:05:43 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-15 13:21:37 +0000 |
| commit | 3b90603668dce79848cd349720fee4b1c1c009cf (patch) | |
| tree | a516d1f62fbcddaab875e80dc3bd56b666ca8375 /src | |
| parent | 331d71bad8290c43f6ac95ea580f848209d6a79b (diff) | |
| download | coreboot-3b90603668dce79848cd349720fee4b1c1c009cf.tar.xz | |
nb/intel/sandybridge: refactor lane_registers[]
Rename array and use defines for the values.
The patch doesn't change the resulting binary when using BUILD_TIMELESS=1
Change-Id: I774373d231a0f4a2fe82ab7c6f1318fc56bcc678
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 29 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/sandybridge.h | 11 |
2 files changed, 23 insertions, 17 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 795775c601..485154287c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1040,10 +1040,10 @@ void dram_mrscommands(ramctr_timing *ctrl) } } -static const u32 lane_registers[] = { - 0x0000, 0x0200, 0x0400, 0x0600, - 0x1000, 0x1200, 0x1400, 0x1600, - 0x0800 +static const u32 lane_base[] = { + LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, + LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, + LANEBASE_ECC }; void program_timings(ramctr_timing *ctrl, int channel) @@ -1155,9 +1155,7 @@ void program_timings(ramctr_timing *ctrl, int channel) shift_402x) << (8 * slotrank); FOR_ALL_LANES { - MCHBAR32(lane_registers[lane] + 0x10 + channel * 0x100 + - 4 * slotrank) - = + MCHBAR32(lane_base[lane] + 0x10 + channel * 0x100 + 4 * slotrank) = (((ctrl->timings[channel][slotrank].lanes[lane]. timA + shift) & 0x3f) | @@ -1170,9 +1168,7 @@ void program_timings(ramctr_timing *ctrl, int channel) | ((ctrl->timings[channel][slotrank].lanes[lane]. falling + shift) << 20)); - MCHBAR32(lane_registers[lane] + 0x20 + channel * 0x100 + - 4 * slotrank) - = + MCHBAR32(lane_base[lane] + 0x20 + channel * 0x100 + 4 * slotrank) = (((ctrl->timings[channel][slotrank].lanes[lane]. timC + shift) & 0x3f) | @@ -1232,7 +1228,7 @@ static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; - return ((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 + + return ((MCHBAR32(lane_base[lane] + channel * 0x100 + 4 + ((timA / 32) & 1) * 4) >> (timA % 32)) & 1); } @@ -1894,7 +1890,7 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) FOR_ALL_LANES { statistics[lane][timB] = - !((MCHBAR32(lane_registers[lane] + + !((MCHBAR32(lane_base[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); } @@ -2017,9 +2013,8 @@ static void adjust_high_timB(ramctr_timing *ctrl) wait_for_iosav(channel); FOR_ALL_LANES { - u64 res = MCHBAR32(lane_registers[lane] + channel * 0x100 + 4); - res |= ((u64) MCHBAR32(lane_registers[lane] + - channel * 0x100 + 8)) << 32; + u64 res = MCHBAR32(lane_base[lane] + channel * 0x100 + 4); + res |= ((u64) MCHBAR32(lane_base[lane] + channel * 0x100 + 8)) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; @@ -3025,9 +3020,9 @@ void write_controller_mr(ramctr_timing *ctrl) int channel, slotrank; FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - MCHBAR32(0x0004 + channel * 0x100 + lane_registers[slotrank]) = + MCHBAR32(0x0004 + channel * 0x100 + lane_base[slotrank]) = make_mr0(ctrl, slotrank); - MCHBAR32(0x0008 + channel * 0x100 + lane_registers[slotrank]) = + MCHBAR32(0x0008 + channel * 0x100 + lane_base[slotrank]) = make_mr1(ctrl, slotrank, channel); } } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index f12feaa158..53fb3eb9b0 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -133,6 +133,17 @@ enum platform_type { #define Cx(r, x) ((r) + ((x) * 0x400)) #define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4)) +/* byte lane training register base addresses */ +#define LANEBASE_B0 0x0000 +#define LANEBASE_B1 0x0200 +#define LANEBASE_B2 0x0400 +#define LANEBASE_B3 0x0600 +#define LANEBASE_B4 0x1000 +#define LANEBASE_B5 0x1200 +#define LANEBASE_B6 0x1400 +#define LANEBASE_B7 0x1600 +#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ + /* Register definitions */ #define GDCRCLKRANKSUSED_ch(ch) Gz(0x0c00, ch) /* Indicates which rank is populated */ #define GDCRCLKCOMP_ch(ch) Gz(0x0c04, ch) /* RCOMP result register */ |