diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-04-02 11:34:59 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-04-11 02:19:30 +0000 |
| commit | 445368cdde3f450a767f05555108db3c09cf531b (patch) | |
| tree | 4ea56eca10bffd54d1d9110b47aee0aec3051d57 /src | |
| parent | f952983b3736a49fc7281cf94cf916b64370e9fb (diff) | |
| download | coreboot-445368cdde3f450a767f05555108db3c09cf531b.tar.xz | |
soc/intel/common: Configure all possible GFX DSM memory reserve range
Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB
This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.
Note: Today all existing SoCs(except Cannonlake) are supported under intel
common code block design may not need to use any other values than 0x0-0x05
for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for
early SoC samples and validation requirement. This code block to justify
all differnet possible ranges that FSP may support for a platform.
TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.
Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/common/block/systemagent/systemagent_early.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 4abc15f59a..609e1596c9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -144,9 +144,34 @@ static uint16_t sa_get_ggc_reg(void) return pci_read_config16(SA_DEV_ROOT, GGC); } +/* + * Internal Graphics Pre-allocated Memory - As per Intel FSP UPD Header + * definition, size of memory preallocatred for internal graphics can be + * configured based on below lists: + * + * 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, + * 0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, + * 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, + * 0xFE:60MB + * + * Today all existing SoCs(except Cannonlake) are supported under intel + * common code block design may not need to use any other values than 0x0-0x05 + * for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for + * early SoC samples and validation requirement. This code block to justify + * all differnet possible ranges that FSP may support for a platform. + */ size_t sa_get_dsm_size(void) { - return (((sa_get_ggc_reg() & G_GMS_MASK) >> G_GMS_OFFSET) * 32*MiB); + uint32_t prealloc_memory; + uint16_t ggc; + + ggc = sa_get_ggc_reg(); + prealloc_memory = (ggc & G_GMS_MASK) >> G_GMS_OFFSET; + + if (prealloc_memory < 0xF0) + return prealloc_memory * 32*MiB; + else + return (prealloc_memory - 0xEF) * 4*MiB; } static uintptr_t sa_get_gsm_base(void) |