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authorJoel Kitching <kitching@google.com>2018-08-17 15:38:59 +0800
committerMartin Roth <martinroth@google.com>2018-08-22 15:33:50 +0000
commit44cff7a8975b2adbf2866718ec8c61ab0d9bd505 (patch)
tree92d4975db05b7dde5b861f03e5ee3c65bbb6b661 /src
parent5846d5727a05e395d13317daba049e0e56e15d33 (diff)
downloadcoreboot-44cff7a8975b2adbf2866718ec8c61ab0d9bd505.tar.xz
cbtable: remove chromeos_acpi from cbtable
Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/commonlib/include/commonlib/coreboot_tables.h1
-rw-r--r--src/lib/coreboot_table.c16
-rw-r--r--src/soc/amd/stoneyridge/include/soc/nvs.h2
-rw-r--r--src/soc/intel/apollolake/include/soc/nvs.h2
-rw-r--r--src/soc/intel/baytrail/include/soc/device_nvs.h3
-rw-r--r--src/soc/intel/baytrail/include/soc/nvs.h2
-rw-r--r--src/soc/intel/braswell/include/soc/device_nvs.h3
-rw-r--r--src/soc/intel/braswell/include/soc/nvs.h2
-rw-r--r--src/soc/intel/broadwell/include/soc/device_nvs.h3
-rw-r--r--src/soc/intel/broadwell/include/soc/nvs.h2
-rw-r--r--src/soc/intel/cannonlake/include/soc/nvs.h2
-rw-r--r--src/soc/intel/fsp_baytrail/include/soc/device_nvs.h3
-rw-r--r--src/soc/intel/skylake/include/soc/device_nvs.h3
-rw-r--r--src/soc/intel/skylake/include/soc/nvs.h2
-rw-r--r--src/southbridge/intel/bd82x6x/nvs.h2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/nvs.h2
-rw-r--r--src/southbridge/intel/fsp_i89xx/nvs.h2
-rw-r--r--src/southbridge/intel/ibexpeak/nvs.h2
-rw-r--r--src/southbridge/intel/lynxpoint/nvs.h2
-rw-r--r--src/vendorcode/google/chromeos/gnvs.h12
20 files changed, 24 insertions, 44 deletions
diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h
index 34726abab3..6ca0f779aa 100644
--- a/src/commonlib/include/commonlib/coreboot_tables.h
+++ b/src/commonlib/include/commonlib/coreboot_tables.h
@@ -290,7 +290,6 @@ struct lb_gpios {
struct lb_gpio gpios[0];
};
-#define LB_TAG_CHROMEOS_ACPI 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 6b0e1a0237..62b3aaa82b 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -195,19 +195,6 @@ static void lb_gpios(struct lb_header *header)
}
}
-static void lb_chromeos_acpi(struct lb_header *header)
-{
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- struct lb_range *chromeos_acpi;
-
- chromeos_acpi = (struct lb_range *)lb_new_record(header);
- chromeos_acpi->tag = LB_TAG_CHROMEOS_ACPI;
- chromeos_acpi->size = sizeof(*chromeos_acpi);
- acpi_get_chromeos_acpi_info(&chromeos_acpi->range_start,
- &chromeos_acpi->range_size);
-#endif
-}
-
static void lb_vbnv(struct lb_header *header)
{
#if IS_ENABLED(CONFIG_PC80_SYSTEM)
@@ -547,9 +534,6 @@ static uintptr_t write_coreboot_table(uintptr_t rom_table_end)
/* Record our GPIO settings (ChromeOS specific) */
lb_gpios(head);
- /* pass along the chromeos_acpi_t buffer address */
- lb_chromeos_acpi(head);
-
/* pass along VBNV offsets in CMOS */
lb_vbnv(head);
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index b4f7213eca..bcac3a9d8c 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -55,6 +55,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* __SOC_STONEYRIDGE_NVS_H__ */
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index c7be979553..3250aeb277 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -53,6 +53,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/device_nvs.h b/src/soc/intel/baytrail/include/soc/device_nvs.h
index b4fe65e7d9..bc6f7ec5de 100644
--- a/src/soc/intel/baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/baytrail/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index 21cdb142a4..715929d7ea 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -102,7 +102,7 @@ typedef struct global_nvs_t {
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index 268655e7cb..8ed534eb91 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -20,9 +20,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 89a434bf8b..05831bb7d1 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -106,7 +106,7 @@ typedef struct global_nvs_t {
/* LPSS (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#if ENV_SMM
diff --git a/src/soc/intel/broadwell/include/soc/device_nvs.h b/src/soc/intel/broadwell/include/soc/device_nvs.h
index 15240d13b4..d17b3d461e 100644
--- a/src/soc/intel/broadwell/include/soc/device_nvs.h
+++ b/src/soc/intel/broadwell/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define SIO_NVS_DMA 0
#define SIO_NVS_I2C0 1
#define SIO_NVS_I2C1 2
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 34673d55bc..2e51e1bd20 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -94,7 +94,7 @@ typedef struct global_nvs_t {
/* Device specific (0x1000) */
device_nvs_t dev;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
void acpi_create_gnvs(global_nvs_t *gnvs);
#ifdef __SMM__
diff --git a/src/soc/intel/cannonlake/include/soc/nvs.h b/src/soc/intel/cannonlake/include/soc/nvs.h
index 6c64f3ac2c..1e5562566d 100644
--- a/src/soc/intel/cannonlake/include/soc/nvs.h
+++ b/src/soc/intel/cannonlake/include/soc/nvs.h
@@ -46,7 +46,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
index 5bafea6fd0..8eff8cdb6f 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/device_nvs.h
@@ -19,9 +19,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define LPSS_NVS_SIO_DMA1 0
#define LPSS_NVS_I2C1 1
#define LPSS_NVS_I2C2 2
diff --git a/src/soc/intel/skylake/include/soc/device_nvs.h b/src/soc/intel/skylake/include/soc/device_nvs.h
index 02c9e65809..2b7d1267fc 100644
--- a/src/soc/intel/skylake/include/soc/device_nvs.h
+++ b/src/soc/intel/skylake/include/soc/device_nvs.h
@@ -20,9 +20,6 @@
#include <stdint.h>
#include <compiler.h>
-/* Offset in Global NVS where this structure lives */
-#define DEVICE_NVS_OFFSET 0x1000
-
#define SIO_NVS_I2C0 0
#define SIO_NVS_I2C1 1
#define SIO_NVS_I2C2 2
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index bd3610e654..53fdded8e9 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -102,6 +102,6 @@ typedef struct global_nvs_t {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 207f763cee..537139dde1 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -154,7 +154,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h
index a0e063c393..c8af5b989a 100644
--- a/src/southbridge/intel/fsp_bd82x6x/nvs.h
+++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h
@@ -150,7 +150,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/fsp_i89xx/nvs.h b/src/southbridge/intel/fsp_i89xx/nvs.h
index a0e063c393..c8af5b989a 100644
--- a/src/southbridge/intel/fsp_i89xx/nvs.h
+++ b/src/southbridge/intel/fsp_i89xx/nvs.h
@@ -150,7 +150,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
index 870391183f..7b9fd249fc 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -152,7 +152,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index e7d4a8b2d8..fd0d8bc961 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -128,7 +128,7 @@ typedef struct global_nvs_t {
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, 0x100);
+check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#ifdef __SMM__
/* Used in SMM to find the ACPI GNVS address */
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index e865c0e832..62fa08c5f2 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -41,6 +41,18 @@
#define ACTIVE_ECFW_RO 0
#define ACTIVE_ECFW_RW 1
+/*
+ * chromeos_acpi_t portion of ACPI GNVS is assumed to live at
+ * 0x100 - 0x1000. When defining global_nvs_t, use check_member
+ * to ensure that it is properly aligned:
+ *
+ * check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+ */
+#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
+
+/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */
+#define GNVS_DEVICE_NVS_OFFSET 0x1000
+
typedef struct {
/* ChromeOS specific */
u32 vbt0; // 00 boot reason