soc/intel/tigerlake: add support to read SPD data from SMBus

Jasper Lake RVP has DDR4 variant which uses SMBus address to read SPD
data. So, add support to read SPD data from SMBUS.

BUG=None
BRANCH=None
TEST=Check compilation for Jasper Lake RVP and check memory training passes.

Change-Id: I94f8707c731c8afa1106e387a246c000bd53a654
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39401
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 25 insertions, 11 deletions

diff --git a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h
index b828ae1cdf..421e31d8e4 100644
--- a/src/soc/intel/tigerlake/include/soc/meminit_jsl.h
+++ b/src/soc/intel/tigerlake/include/soc/meminit_jsl.h
@@ -27,6 +27,9 @@
 /* Number of DQ byte mappings */
 #define DDR_NUM_BYTE_MAPPINGS 6
 
+/* Number of memory DIMM slots available on Jasper Lake */
+#define NUM_DIMM_SLOT 4
+
 /* 64-bit Channel identification */
 enum {
 	DDR_CH0,
@@ -40,17 +43,21 @@ struct spd_by_pointer {
 };
 
 enum mem_info_read_type {
-	READ_SPD_CBFS,	/* Find spd file in CBFS. */
-	READ_SPD_MEMPTR	/* Find spd data from pointer. */
+	READ_SPD_CBFS,	/* Find SPD file in CBFS. */
+	READ_SMBUS,	/* Read on-module SPD by SMBUS. */
+	READ_SPD_MEMPTR	/* Find SPD data from pointer. */
 };
 
 struct spd_info {
 	enum mem_info_read_type read_type;
 	union spd_data_by {
-		/* To identify spd file when read_type is READ_SPD_CBFS. */
+		/* To read on-module SPD when read_type is READ_SMBUS. */
+		uint8_t spd_smbus_address[NUM_DIMM_SLOT];
+
+		/* To identify SPD file when read_type is READ_SPD_CBFS. */
 		int spd_index;
 
-		/* To find spd data when read_type is READ_SPD_MEMPTR. */
+		/* To find SPD data when read_type is READ_SPD_MEMPTR. */
 		struct spd_by_pointer spd_data_ptr_info;
 	} spd_spec;
 };
diff --git a/src/soc/intel/tigerlake/meminit_jsl.c b/src/soc/intel/tigerlake/meminit_jsl.c
index 3247357f1a..c68d2100fc 100644
--- a/src/soc/intel/tigerlake/meminit_jsl.c
+++ b/src/soc/intel/tigerlake/meminit_jsl.c
@@ -102,15 +102,22 @@ static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_c
 void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
 			const struct spd_info *spd_info, bool half_populated)
 {
-	size_t spd_data_len;
-	uintptr_t spd_data_ptr;
 
-	memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable));
-	get_spd_data(spd_info, &spd_data_ptr, &spd_data_len);
-	print_spd_info((unsigned char *)spd_data_ptr);
+	if (spd_info->read_type == READ_SMBUS) {
+		for (int i = 0; i < NUM_DIMM_SLOT; i++)
+			mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i];
 
-	mem_cfg->MemorySpdDataLen = spd_data_len;
-	meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
+		meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated);
+	} else {
+		uintptr_t spd_data_ptr = 0;
+		size_t spd_data_len = 0;
+		memset(&mem_cfg->SpdAddressTable, 0, sizeof(mem_cfg->SpdAddressTable));
+		get_spd_data(spd_info, &spd_data_ptr, &spd_data_len);
+		print_spd_info((unsigned char *)spd_data_ptr);
+
+		mem_cfg->MemorySpdDataLen = spd_data_len;
+		meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated);
+	}
 
 	/* Early Command Training Enabled */
 	mem_cfg->ECT = board_cfg->ect;