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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-04 01:59:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-12-05 09:44:23 +0000 |
| commit | 455d7b74abdcc05ead46e1b4ca0f969df4f9a025 (patch) | |
| tree | 6f4a1b3fe8d4a5105d13f968e3f9f1b7c96d4761 /src | |
| parent | c6ef514e93734baafb5e613982dc3b249497960e (diff) | |
| download | coreboot-455d7b74abdcc05ead46e1b4ca0f969df4f9a025.tar.xz | |
soc/amd/picasso/tsc: fix clock divisor range check
The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.
TEST=Compared with Picasso's PPR #55570
Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/picasso/tsc_freq.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 8a541fc4a2..55c86653ce 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -33,7 +33,7 @@ unsigned long tsc_freq_mhz(void) if (!cpudid) { mhz = TSC_DEFAULT_FREQ_MHZ; printk(BIOS_ERR, "Invalid divisor, set TSC frequency to %ldMHz\n", mhz); - } else if ((cpudid >= 8) && (cpudid < 0x3c)) { + } else if ((cpudid >= 8) && (cpudid <= 0x30)) { mhz = (200 * cpufid) / cpudid; } else { mhz = 25 * cpufid; |