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| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-03-20 21:12:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-22 11:32:09 +0000 |
| commit | 480c2de54944ce733dbbfe097c774c3369fc2374 (patch) | |
| tree | 5b86d3b109efc6772d42d2adaf74b9c6927c7007 /src | |
| parent | 023fdaffd14f7d3d70a81041bf76095fb50869f8 (diff) | |
| download | coreboot-480c2de54944ce733dbbfe097c774c3369fc2374.tar.xz | |
purism/librem_14: add on-board LAN device
On-board devices should be present in the devicetree, so that
`.on_mainboard` field of `struct device` is `1`.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3678514482724377bcdfcbdc7f2c5b312a48b2c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb index dc89bd4263..375aa5dfcc 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb @@ -229,7 +229,8 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[2]" = "2" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end - device pci 1c.7 on # PCI Express Port 8 -- x1 (LAN) + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # x1 (LAN) register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[3]" = "7" register "PcieClkSrcClkReq[3]" = "3" |