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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-05 14:07:32 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-03-07 01:10:57 +0100
commit50bb68f2b684873a15aa52c8f423daa5bae6b776 (patch)
tree349244f825bbda5b28d464c744e01d084f22e475 /src
parentc3c407c62c2809ad0e78094fbc26cbf9612b3855 (diff)
downloadcoreboot-50bb68f2b684873a15aa52c8f423daa5bae6b776.tar.xz
AGESA fam14: Sanitize headerfile
This file is only static defines. Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/amd/inagua/PlatformGnbPcieComplex.h4
-rw-r--r--src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h5
-rw-r--r--src/mainboard/amd/south_station/PlatformGnbPcieComplex.h4
-rw-r--r--src/mainboard/amd/union_station/PlatformGnbPcieComplex.h4
-rw-r--r--src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h4
-rw-r--r--src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h5
-rw-r--r--src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h5
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h3
-rw-r--r--src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h5
-rw-r--r--src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h5
-rw-r--r--src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h5
11 files changed, 0 insertions, 49 deletions
diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
index 60045e1839..30f674a33b 100644
--- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h
@@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
index 4132c7c210..0342e8ebd6 100644
--- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h
@@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
index 001ed169e7..ee8e4996f9 100644
--- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h
@@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
index 001ed169e7..ee8e4996f9 100644
--- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
+++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h
@@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
index 001ed169e7..ee8e4996f9 100644
--- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
+++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h
@@ -16,10 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h
index 0f3fdc6b92..0bea8970e9 100644
--- a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h
+++ b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h
@@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
/*
* GNB GPP Port4
* GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable
diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h
index 66618ae451..acdb6557c2 100644
--- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h
+++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h
@@ -17,11 +17,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
index a91bd0f2c2..782f5c234a 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
@@ -17,9 +17,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include <vendorcode/amd/agesa/f14/AGESA.h>
-#include <amdlib.h>
-
/**
* @brief Graphic NorthBridge (GNB) General Purpose Port (GPP)
*
diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h
index 9f99f32a72..0f0b41bf0f 100644
--- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h
+++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h
@@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h
index 50c8f088f7..017ea77fc0 100644
--- a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h
+++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h
@@ -16,11 +16,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2
diff --git a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h
index bb4ba8628f..64adf5cdde 100644
--- a/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h
+++ b/src/mainboard/pcengines/apu1/PlatformGnbPcieComplex.h
@@ -17,11 +17,6 @@
#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H
#define _PLATFORM_GNB_PCIE_COMPLEX_H
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include <cpu/amd/agesa/s3_resume.h>
-
//GNB GPP Port4
#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable
#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2