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authorWim Vervoorn <wvervoorn@eltan.com>2020-05-07 13:21:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-05-18 07:10:48 +0000
commit544cc834700590c6c804150f1db81ee31a3bbd30 (patch)
tree6d6ed7e06b329bcd634204e7bb8a6d8e11449805 /src
parentd0ded1652927016677e366e2cc8a112a60db251a (diff)
downloadcoreboot-544cc834700590c6c804150f1db81ee31a3bbd30.tar.xz
mb/facebookmonolith: Update root port settings
Update monolith root port settings to match those of the original BIOS. MaxPayload is set to 256 bytes, ASPM is disabled and LTR and Advanced Error reporting are enabled. BUG=N/A TEST=tested on facebook monolith Change-Id: Idf6e706d45cf1ea1aee4a75a6d0eb130b21db927 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/facebook/monolith/devicetree.cb24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb
index 45829aac1f..102450a77a 100644
--- a/src/mainboard/facebook/monolith/devicetree.cb
+++ b/src/mainboard/facebook/monolith/devicetree.cb
@@ -161,6 +161,14 @@ chip soc/intel/skylake
register "PcieRpEnable[2]" = "1"
# Disable CLKREQ#
register "PcieRpClkReqSupport[2]" = "0"
+ # Set MaxPayload to 256 bytes
+ register "PcieRpMaxPayload[2]" = "RpMaxPayload_256"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[2]" = "1"
+ # Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[2]" = "1"
+ # Disable Aspm
+ register "PcieRpAspm[2]" = "AspmDisabled"
# PCIE Port 4 disabled
# PCIE Port 5 x1 -> MODULE i219
@@ -168,6 +176,14 @@ chip soc/intel/skylake
# PCIE Port 6 x1 -> BASEBOARD x1 i210 : Mapped to PCIe 4 on the baseboard
register "PcieRpEnable[5]" = "1"
register "PcieRpClkReqSupport[5]" = "0"
+ # Set MaxPayload to 256 bytes
+ register "PcieRpMaxPayload[5]" = "RpMaxPayload_256"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[5]" = "1"
+ # Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[5]" = "1"
+ # Disable Aspm
+ register "PcieRpAspm[5]" = "AspmDisabled"
# PCIE Port 7 Disabled
# PCIE Port 8 Disabled
@@ -178,6 +194,14 @@ chip soc/intel/skylake
register "PcieRpClkReqSupport[8]" = "0"
# Use Hot Plug subsystem
register "PcieRpHotPlug[8]" = "1"
+ # Set MaxPayload to 256 bytes
+ register "PcieRpMaxPayload[8]" = "RpMaxPayload_256"
+ # Enable Latency Tolerance Reporting Mechanism
+ register "PcieRpLtrEnable[8]" = "1"
+ # Enable Advanced Error Reporting
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ # Disable Aspm
+ register "PcieRpAspm[8]" = "AspmDisabled"
# USB 2.0 Enable all ports
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C Port 2