diff options
| author | Ronald G. Minnich <rminnich@gmail.com> | 2016-10-28 15:08:59 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-02 19:01:42 +0100 |
| commit | 571c2302525206715c2f12bc14fab931e8cdf757 (patch) | |
| tree | 625872744019cc769aeee4a850f24920bbfc68ea /src | |
| parent | c98629cd676b41938978f3e108d54755e3c5935b (diff) | |
| download | coreboot-571c2302525206715c2f12bc14fab931e8cdf757.tar.xz | |
riscv: Add a bandaid for the new toolchain
After I did a new toolchain build, I found the
the mhartid register value is wrong for Spike.
The docs seem to agree with Spike, not the
code the toolchain produces?
Until such time as the bitstreams and toolchain can find
a way to agree, just hardcode it. We've been playing this game
for two years now so this is hardly a new approach.
This is intentionally ugly because we really need the
toolchains and emulators and bitstreams to sync up,
and that's not happening yet. Lowrisc
allegedly implements the v1.9 spec but it's PTEs are clearly
1.7. Once it all settles down we can just use constants
supplied by the toolchain.
I hope the syncup will have happened by the workshop in November.
This gets spike running again.
Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/17183
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/riscv/bootblock.S | 6 | ||||
| -rw-r--r-- | src/arch/riscv/trap_handler.c | 2 | ||||
| -rw-r--r-- | src/arch/riscv/trap_util.S | 4 |
3 files changed, 9 insertions, 3 deletions
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 63df92bb38..c54c0e235c 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -32,7 +32,11 @@ _start: # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE - csrr a0, mhartid + // Once again, the docs and toolchain disagree. + // Rather than get fancy I'll just lock this down + // until it all stabilizes. + //csrr a0, mhartid + csrr a0, 0xf14 call hls_init # poison the stack diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad4992803c..8c69366ba8 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -29,7 +29,7 @@ void handle_supervisor_call(trapframe *tf) { switch(call) { case SBI_ECALL_HART_ID: printk(BIOS_DEBUG, "Getting hart id...\n"); - returnValue = read_csr(mhartid); + returnValue = read_csr(0xf14);//mhartid); break; case SBI_ECALL_NUM_HARTS: /* TODO: parse the hardware-supplied config string and diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 5ee0fddc53..33579590dc 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -119,7 +119,9 @@ trap_entry: # SMP isn't supported yet, to avoid overwriting the same stack with different # harts that handle traps at the same time. - csrr sp, mhartid + # someday this gets fixed. + //csrr sp, mhartid + csrr sp, 0xf14 .Lsmp_hang: bnez sp, .Lsmp_hang |