diff options
| author | John Zhao <john.zhao@intel.com> | 2020-07-28 12:51:53 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2020-07-29 22:46:45 +0000 |
| commit | 5fdf2760a5952df22e5b331bc4f62082d8cec1bc (patch) | |
| tree | c62a5da01564666de47a4b0f2f4246a4e76b21f0 /src | |
| parent | bd615d6f9379cc454c728c8f79f13612f3fb7a19 (diff) | |
| download | coreboot-5fdf2760a5952df22e5b331bc4f62082d8cec1bc.tar.xz | |
mb/google/volteer: Update TCSS D3Hot and D3Cold configuration
It is expected TCSS D3Hot is enabled. D3Cold configuration is
through SoC stepping determination. D3Cold is disabled on pre-QS
platform and enabled on QS platform.
BUG=None
TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 0e8ad3e17a..53bbe5a0c0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -170,10 +170,6 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[6]" = "0x09000000" register "IomTypeCPortPadCfg[7]" = "0x09000000" - # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "0" - # DP port register "DdiPortAConfig" = "1" # eDP register "DdiPortBConfig" = "0" |