summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorStefan Reinauer <stefan.reinauer@coreboot.org>2016-02-24 13:25:42 -0800
committerMartin Roth <martinroth@google.com>2016-03-12 22:03:42 +0100
commit63db6142b6198fc3d6660e58228eeedd2eac59bd (patch)
tree7279968a37b716ded95b62f010293c12857b951f /src
parent2d987fe0fbd2c5271e7b9c4a183558cb6f4dc35a (diff)
downloadcoreboot-63db6142b6198fc3d6660e58228eeedd2eac59bd.tar.xz
northbridge/intel/i82830: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage, select UDELAY_IO for all i830 boards in the chipset. Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/13783 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/rca/rm4100/Kconfig1
-rw-r--r--src/mainboard/rca/rm4100/gpio.c2
-rw-r--r--src/mainboard/rca/rm4100/romstage.c1
-rw-r--r--src/mainboard/thomson/ip1000/Kconfig1
-rw-r--r--src/mainboard/thomson/ip1000/gpio.c2
-rw-r--r--src/mainboard/thomson/ip1000/romstage.c1
-rw-r--r--src/northbridge/intel/i82830/Kconfig1
7 files changed, 5 insertions, 4 deletions
diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig
index a6f216eec1..81cfc7b999 100644
--- a/src/mainboard/rca/rm4100/Kconfig
+++ b/src/mainboard/rca/rm4100/Kconfig
@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_I82801DX
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_PIRQ_TABLE
- select UDELAY_TSC
select BOARD_ROMSIZE_KB_1024
config MAINBOARD_DIR
diff --git a/src/mainboard/rca/rm4100/gpio.c b/src/mainboard/rca/rm4100/gpio.c
index 89c86a3137..a2dac0a334 100644
--- a/src/mainboard/rca/rm4100/gpio.c
+++ b/src/mainboard/rca/rm4100/gpio.c
@@ -14,6 +14,8 @@
* GNU General Public License for more details.
*/
+#include <delay.h>
+
#define PME_DEV PNP_DEV(0x2e, 0x0a)
#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c
index bec4be822f..296d072e23 100644
--- a/src/mainboard/rca/rm4100/romstage.c
+++ b/src/mainboard/rca/rm4100/romstage.c
@@ -19,7 +19,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include "drivers/pc80/udelay_io.c"
#include <console/console.h>
#include <lib.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig
index f775e2bd38..1c21ace453 100644
--- a/src/mainboard/thomson/ip1000/Kconfig
+++ b/src/mainboard/thomson/ip1000/Kconfig
@@ -7,7 +7,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_I82801DX
select SUPERIO_SMSC_SMSCSUPERIO
select HAVE_PIRQ_TABLE
- select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
select INTEL_INT15
diff --git a/src/mainboard/thomson/ip1000/gpio.c b/src/mainboard/thomson/ip1000/gpio.c
index 8a03f73d6f..29c222d2de 100644
--- a/src/mainboard/thomson/ip1000/gpio.c
+++ b/src/mainboard/thomson/ip1000/gpio.c
@@ -14,6 +14,8 @@
* GNU General Public License for more details.
*/
+#include <delay.h>
+
#define PME_DEV PNP_DEV(0x2e, 0x0a)
#define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */
#define ICH_IO_BASE_ADDR 0x00000500 /* GPIO base address register */
diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c
index 2c697915b8..5bb7718cad 100644
--- a/src/mainboard/thomson/ip1000/romstage.c
+++ b/src/mainboard/thomson/ip1000/romstage.c
@@ -19,7 +19,6 @@
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
-#include "drivers/pc80/udelay_io.c"
#include <console/console.h>
#include <lib.h>
#include <superio/smsc/smscsuperio/smscsuperio.h>
diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig
index 25a9e97587..344dfedca8 100644
--- a/src/northbridge/intel/i82830/Kconfig
+++ b/src/northbridge/intel/i82830/Kconfig
@@ -2,6 +2,7 @@ config NORTHBRIDGE_INTEL_I82830
bool
select HAVE_DEBUG_RAM_SETUP
select LATE_CBMEM_INIT
+ select UDELAY_IO
choice
prompt "Onboard graphics"