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authorSugnan Prabhu S <sugnan.prabhu.s@intel.com>2020-08-21 18:05:17 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-08-26 07:31:06 +0000
commit65993e8233f8bb54cb4d6967d018f8c97ba8a4fc (patch)
tree955a37c5a39c0db0b56a2a480142bdb81a4268fe /src
parent4ddbc8b6ed5d05bbf57602a08538c7d58f3a466d (diff)
downloadcoreboot-65993e8233f8bb54cb4d6967d018f8c97ba8a4fc.tar.xz
mb/intel/jasperlake_rvp: Enable I2C4 for UFC
This change updates devicetree to enable I2C4 bus required for the UFC Change-Id: Iade1b64fa3dc890a896fb987fdc8d68db7db5e5f Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 268d239c06..b779d00c75 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -94,7 +94,7 @@ chip soc/intel/jasperlake
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
- [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
}"
@@ -149,6 +149,9 @@ chip soc/intel/jasperlake
.sda_hold = 36,
}
},
+ .i2c[4] = {
+ .speed = I2C_SPEED_FAST,
+ },
.i2c[5] = {
.speed = I2C_SPEED_FAST,
},