diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-11-01 14:19:24 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-03-11 19:54:04 +0100 |
| commit | 65ad521f8a19ec42c1bafa6777eb927fa55261a2 (patch) | |
| tree | d66fd55a1ed9a21ddc69aba596329f498ccd35c5 /src | |
| parent | 46ab8cdc680cdafe37532b9ee15d38efa4912c98 (diff) | |
| download | coreboot-65ad521f8a19ec42c1bafa6777eb927fa55261a2.tar.xz | |
baytrail: add ccu iosf access functions
The clock control unit needs to be accessed to configure
some of the devices properly. Therefore. provide a way
to access the CCU.
BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built.
Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175492
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4927
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/baytrail/baytrail/iosf.h | 18 | ||||
| -rw-r--r-- | src/soc/intel/baytrail/iosf.c | 14 |
2 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 9b59fbc99d..83e03a5a8c 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -70,6 +70,8 @@ uint32_t iosf_ushphy_read(int reg); void iosf_ushphy_write(int reg, uint32_t val); uint32_t iosf_lpss_read(int reg); void iosf_lpss_write(int reg, uint32_t val); +uint32_t iosf_ccu_read(int reg); +void iosf_ccu_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -86,6 +88,7 @@ void iosf_lpss_write(int reg, uint32_t val); #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ +#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ /* Read and write opcodes differ per port. */ #define IOSF_OP_READ_AUNIT 0x10 @@ -112,6 +115,8 @@ void iosf_lpss_write(int reg, uint32_t val); #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 #define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) +#define IOSF_OP_READ_CCU 0x06 +#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) /* @@ -195,5 +200,18 @@ void iosf_lpss_write(int reg, uint32_t val); # define LPSS_CTL_NOSNOOP (1 << 19) # define LPSS_CTL_PM_CAP_PRSNT (1 << 1) +/* + * CCU Registers + */ + +#define PLT_CLK_CTRL_0 0x3c +#define PLT_CLK_CTRL_1 0x40 +#define PLT_CLK_CTRL_2 0x44 +#define PLT_CLK_CTRL_3 0x48 +#define PLT_CLK_CTRL_4 0x4c +#define PLT_CLK_CTRL_5 0x50 +# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) +# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) +# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index a7f7a905bc..7e0dacb812 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -154,3 +154,17 @@ void iosf_lpss_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_LPSS); return iosf_write_port(cr, reg, val); } + +uint32_t iosf_ccu_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_CCU) | + IOSF_PORT(IOSF_PORT_CCU); + return iosf_read_port(cr, reg); +} + +void iosf_ccu_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_CCU) | + IOSF_PORT(IOSF_PORT_CCU); + return iosf_write_port(cr, reg, val); +} |